17:06 <agg> do I need 2FFs on signals that are async but I only look at them when I know they're valid?

17:07 <agg> I have an external parallel input bus, I'm registering it in the IO cell to ensure it's sampled at the same time on all bits, but then the input signal goes to a couple of modules that use the data; separately I know from timing of a control signal when the bus is valid

17:08 <agg> but the IO cell register could be metastable for some clock periods where I'm not using it

17:10 <agg> (I appreciate normally 2FFs aren't used on a parallel bus because you can't be sure you got all the bits on the same clock cycle, so you need to use 2FFs to synchronise handshake signals and then sample the bus after the handshake; my question is basically whether I should still also have 2FF on the data signals given the bus is sampled on every clock including when it might not be valid)

17:10 <agg> I guess a better approach might be to drive the IO cell register with the valid signal instead...