omnitechnomancer has quit [Quit: Idle for 30+ days]
lopsided98 has joined ##openfpga
lopsided98_ has quit [Ping timeout: 276 seconds]
specing_ has joined ##openfpga
specing has quit [Ping timeout: 268 seconds]
specing_ is now known as specing
GenTooMan has quit [Ping timeout: 250 seconds]
Sellerie has quit [Read error: Connection reset by peer]
GenTooMan has joined ##openfpga
sgstair has quit [Ping timeout: 252 seconds]
sgstair_ has joined ##openfpga
sgstair_ is now known as sgstair
cpresser has joined ##openfpga
sgstair has quit [Read error: Connection reset by peer]
sgstair has joined ##openfpga
<balrog>
has anyone done any work on xilinx xc4000 family?
<mwk>
I've done a little feasibility study of reversing it
<mwk>
conclusion: annoying due to being loads and loads of variants, timing is a major pain due to unbuffered interconnect, obtaining vendor bitstream generation tools for it is likewise pain
<mwk>
≥ xc4000e can be relatively easily blackbox-reversed with ancient windows ISE, older than that and we're entering xactstep territory which is *very* inconvenient to script