<NiteHawk>
KotCzarny_: were you able to confirm/verify the "oddball" SIDs that you got for your OPi PCs? they sure seem a little weird...
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<MoeIcenowy>
thx
<MoeIcenowy>
seems that the regulator has no i2c...
<MoeIcenowy>
how to tweak it?
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<Da_Coynul>
NiteHawk: were you referring to the SID's I got with devmem2? If so, what was "oddball" about them?
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<Amit_T>
is there any way to read arm64 Image 64 bytes header ?
<NiteHawk>
Da_Coynul: no, yours are in line with other results we've got. KotCzarny ("Kc") seems to have SIDs where the first 32-bit value differs from other models of the same SoC family
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<ssvb>
NiteHawk: it's just that the first SID word differs on H3 when read early in U-Boot or via FEL when compared to reading it via devmem2 much later in Linux
<ssvb>
I could also reproduce this but haven't investigated it yet
<ssvb>
basically, we need to figure out when exactly it gets changed
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<ssvb>
and then look at what could have affected it
<NiteHawk>
ssvb: didn't we observe something similar when initially trying to "read" the SID memory directly via sunxi-fel? i'm suspecting we might have another case where byte-oriented access of those values fails - which is why you introduced "readl" in the end
<ssvb>
NiteHawk: it's only the first word getting changed, the others remain the same
<NiteHawk>
ah, right. good point
<ssvb>
this is a little bit inconsistent
<ssvb>
I still would try to track the exact time when this change happens
<ssvb>
Maybe it's the arisc firmware doing something? But we don't know until we investigate this
<plaes>
qschulz: I managed to find some time today to play with your iio patches
<montjoie>
Da_Coynul which uboot versiob give you mac collison ?
<Da_Coynul>
I was getting the MAC collision with 2016.05
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<montjoie>
ssvb: does 2016.05 has your patch ?
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<montjoie>
I believe to remember someone has already said yes
<qschulz>
plaes: could you elaborate more? How did you conclude it was X2 and Y2 that were read?
<plaes>
I ran this shell script: while [ 1 ] ; do cat /sys/devices/platform/soc@01c00000/1c25000.rtp/sun5i-a13-gpadc-iio.0/iio:device0/in_voltage* ; done
<plaes>
and only second and fourth columns (1 and 3) gave me readings
<plaes>
and the pins were X2 and Y2 on CHIP 0x21
<qschulz>
plaes: what was the return of first and third channels (columns)?
<plaes>
firstly, it seemed to be always equal (chan0 == chan2)
<plaes>
and reading was either something like 1856 or 4565 (don't remember exact numbers)
<qschulz>
and what is the output of second and forth channel?
<plaes>
it seemed to be proper voltage (in millivolts)
<qschulz>
plaes: can you test by reading multiple times the same channel? I think I had some problems when switching channels.
<qschulz>
plaes: so you have four sensors plugged on the ADC? One per channel ?
<plaes>
nope, I only tried with one sensor
<qschulz>
plaes: I had a project with IR sensors to get the distance from an object... Do not believe everything that's returned by the sensor, sometimes it is returning unbelievably erroneous values
<plaes>
there I saw also some crosstalk between X2 and Y2
<plaes>
and later I tried with two sensors - X2 and Y2
<plaes>
then it looked better
<plaes>
but I never got any output from X1 and Y1 pins
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<willmore>
MoeIcenowy, did you resolve your Opi1 regulator question?
<willmore>
It's a 'dumb' regulator. There's a GPIO that tells it to go high output or low output. Basically, it alters the resistor settings that set the output voltage.
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