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<lkcl>
ani
<lkcl>
anuejn: unfortunately this is not the case.... and have m.If, m.Else, m.Switch work correctly as expected
<lkcl>
dynamic partitioned SIMD signals require a context that is non-global in nature, but is instead context-sensitive and specific to the PartitionedSignal
<lkcl>
this requirement is in direct conflict with the global definition of nmigen.Mux etc.
<lkcl>
i have been investigating and thinking about this for around 5-7 months, and, after all that time, the changes required are surprisingly small
<lkcl>
once Part / Mux / etc. change to call lhs.part(...), the capability exists to "carry through" the critical context-sensitive information which in the case of PartitionedSignal is... well.. the partition bits.
<lkcl>
without that context-sensitive information. m.If / m.Else and m.Switch literally fall apart.
<lkcl>
*with* that context-sensitive information correctly carried, it works perfectly fine
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<revolve>
in nmigen is there a limit on clock speed? how do I know the top speed something can be taped out at?
<whitequark>
this is not something that a HDL translator can tell you; only downstream tools like nextpnr can
<revolve>
whitequark: thanks. is there one with a python interface?
<revolve>
sorry if this is a dumn question; can something like nextpnr tell me the top clock speed something can be taped out at or just how fast it can be simulated at?
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<vup>
revolve: nextpnr is used for fpga's, so it can tell you the top clock speed for a fpga implementation (for one of the fpga families it supports)
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<revolve>
thanks vup
<revolve>
vup: in the design process how do I determine the speed limit of a taped-out design?
<vup>
that depends on your design flow
<vup>
how do you convert your digital design (for example verilog / vhdl files) into the asic layout?
<revolve>
I'm just starting out
<vup>
ok, usually timing analysis is part of this flow. Which flow you are using strongly depends on which fab / technology you are targeting and the tools you have available.
<revolve>
thanks for you help, vup
<vup>
For example a commonly used proprietary tool is cadence Innovus
<vup>
but there are also free / open source variants
<vup>
there is the openroad flow, which has atleast opensta for timing analysis
<sorear>
"how do I determine the speed limit of a taped-out design" arguably the answer here is "by adjusting the clock up until it misbehaves"; timing analysis tools will tell you a safe clock but they are necessarily conservative
<vup>
and then do a sweep over external factors, like temperature
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<revolve>
thanks. can these tools tell me anything about operating temperature?
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<vup>
Commercial tools certainly can, not sure about opensta for example, but I would assume it can, as its wore about the cell models than the timing analysis part
<revolve>
thanks
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<lkcl>
does anyone know how to assign attributes to a module instance?
<lkcl>
currently the workaround is to include a verilog instance
<vup>
lkcl: is SPBlock_512W64B8W written in nmigen or a instance created with `Instance`
<vup>
?
<vup>
for the latter you can use `a_attrname = value` in the `Instance` constructor
<vup>
for the former a slightly different workaround is converting the submodule to a Fragment and adding the attr there before adding it to `m.submodules`
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<lkcl>
vup: it's a black box which coriolis2 will look for the name, and substitute a hard-coded Cell, rather than use whatever is inside of it (as defined by Yosys)
<lkcl>
m.submodules.a.attrs["test"] = "value"
<lkcl>
ah ha! perfect!
<lkcl>
that's exactly what i need, thank you
<lkcl>
basically, Staf Verhaegen is writing a 4K SRAM cell for Libre-SOC. it therefore has exactly the same interface as $mem but we absolutely cannot let yosys get its hands on the process, it'll make a dog's dinner mess
<lkcl>
the solution we came up with was to have an explicit hard-coded Cell, and a "dummy" verilog module
<lkcl>
the trick of adding the "blackbox=1" attribute is to help coriolis2 to identify it.
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<vup>
I see, makes sense
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<lkcl>
vup: being able to stick in nmigen means we can run nmigen simulations, don't have any $Instance(Verilogs), so was really appreciated the trick about submodule.x.attrs.
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<_whitenotifier>
[nmigen] hellow554 opened issue #588: Left shift + simulator = infinite (?) loop - https://git.io/JtEgb
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<_whitenotifier>
[nmigen] rroohhh commented on issue #588: Left shift + simulator = infinite (?) loop - https://git.io/JtEVv
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<_whitenotifier>
[nmigen] hellow554 commented on issue #588: Left shift + simulator = infinite (?) loop - https://git.io/JtErf
<smkz>
when doing bit_select(a, b) does it output [a, a+b] (inclusive) or [a, a+b) (exclusive)?
<agg>
lkcl: when you create the nmigen Instance you can pass a_blackbox=1 to the Instance constructor alongside like i_input=X and o_output=y (and p_param=z too)
<_whitenotifier>
[nmigen] rroohhh commented on issue #588: Left shift + simulator = infinite (?) loop - https://git.io/JtErY
<vup>
agg: the way I understood it, this is not actually using `Instance`
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<agg>
aah, I see what you mean, it's a Module instance and the resulting verilog module wants the attribute so that the nmigen facsimile is replaced by the special cell, perhaps
<vup>
smkz: exclusive
<vup>
its the equivalent of the 'something[a +: b]` thing from verilog, if you know that