ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each Monday at 1800 UTC · next meeting TBD
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<_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JtdKl
<_whitenotifier-5> [YoWASP/nextpnr] whitequark 31196cb - Update dependencies.
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<_whitenotifier-5> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±2] https://git.io/Jtd6t
<_whitenotifier-5> [YoWASP/yosys] whitequark 1844a6a - Update dependencies.
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<cr1901_modern> https://github.com/nmigen/nmigen/pull/575 I can't really visualize it offhand, but without this PR, is it possible to use OSCH as the default clock (even if it's not convenient)?
<whitequark> well, you could do the changes in your own platform subclass that inherits from whichever platform you want
<cr1901_modern> I might just do that for now. Looking at trying to interface to MachXO2 Embedded Function Block (aka Hard IP) w/ nmigen; it requires the OSCH.
<cr1901_modern> FWIW, the PR I linked, as well as the nmigen board PR linked work fine for me- whenever you have bandwidth to look at it.
<whitequark> you can just instance it yourself
<whitequark> it doesn't have the default clock
<whitequark> *have to be the
* cr1901_modern nods
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<cr1901_modern> This does what I want, for those who are wondering (Diamond only): http://ix.io/2QOV
<d1b2> <benzn> did the nmigen simulator get support for loading verilog files?
<d1b2> <benzn> i see it mentioned in a tweet from 2019
<d1b2> <benzn> i don't see anything in the code that would indicate as such, but wanted to check
<mwk> uh, I don't think anything like this exists
<mwk> it'd be really alien to how nmigen sim works
<mwk> it can, however, be simulated with cxxsim, which is kind of still wip
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<d1b2> <benzn> cool, yeah it did seems surprising
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