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<rqou> wtf
<rqou> vhdl blocks can be generic
<rqou> but why?
<rqou> you can't instantiate blocks
<rqou> can you?
<lain> I... what? they can? I don't know why that would be a thing D:
<rqou> ugh, i think you can have a generic-mapped block inside a generate
<lain> hahahah
<rqou> this language would be so much better if it had "real" macros instead of this giant pile of "stuff"
<lain> yes
<lain> the more I use vhdl the more I understand why people just #yolo their way through verilog. they both suck though, just.. differently :/
<lain> or you can be azonenberg and make verilog more strict through linting and formal vrrification :P
<rqou> i think it also helps explain the prevalence of verilog + <some mess of perl/python/m4/c-preprocessor/sed/whatever>
<lain> yeah
<lain> the thing about vhdl generic stuff is.. even where it is supported, it's usually juuuuust shy of being actually useful; some nonsensical restriction in the spec will break it for whatever use you thought it was good for
<Zarutian> this actually explains why I have seen an domain language based on Scheme to verilog compiler and environment
<Zarutian> basically someone got sick of the crappyness of vhdl and verilog
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<qu1j0t3> Zarutian: there are about a dozen of these now. Python, Scala, Haskell, Ocaml and no doubt other host languages.
<qu1j0t3> Zarutian: Chisel, Obsidian, Lava, Migen, etc
<qu1j0t3> definitely an untapped need here
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