<openfpga-github>
[openfpga] rqou pushed 5 new commits to master: https://git.io/vHFj2
<openfpga-github>
openfpga/master 693c800 Robert Ou: xc2bit: Clean up some code duplication
<openfpga-github>
openfpga/master 277affc Robert Ou: xc2bit: Implement writing IO configuration to crbit
<openfpga-github>
openfpga/master be731db Robert Ou: xc2bit: Write macrocell (but not IO) data to crbit format
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHbJd
<openfpga-github>
openfpga/master 700bb97 Andrew Zonenberg: Fixed addressing in XC2C model. Now supports programming and readback. No support for USERCODE/read lock yet. No support for OTF or SRAM program modes. No actual fabric logic.
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHbkm
<openfpga-github>
openfpga/master 781888a Andrew Zonenberg: XC2CZIA: added initial ZIA structure for 32-macrocell device
<azonenberg>
rqou: also, the ZIA config for the 2c64a in the bitstream is totally wonky
<azonenberg>
in terms of physical layout vs JED
<azonenberg>
sorry i meant, macrocell
<azonenberg>
that is really weird
<azonenberg>
its almost mirrored
<azonenberg>
but not exactly
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vHbqt
<openfpga-github>
openfpga/master b084317 Andrew Zonenberg: XC2C*: Initial tests on 32-macrocell ZIA show it seems to be working
<azonenberg>
Ok, this is progress
<azonenberg>
Gonna try and get the PLAs working before i go to bed
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<azonenberg>
rqou: hmmmm
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<azonenberg>
rqou: also, another thing that threw me off
<azonenberg>
bit ordering for the JTAG addressing is mirrored L-R
<azonenberg>
i.e. gray code of 0,1,2,3,4 is 0, 20, 30, 10, 18, 38, 28...
<azonenberg>
(hex)
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<azonenberg>
hmmmm
<azonenberg>
i wonder if my jtag shift registers are funky
<azonenberg>
because my whole bitfile seems mirrored from what i'd expect
<azonenberg>
rqou: ok so, the ZIA is now working
<azonenberg>
but the AND array is acting funny
<azonenberg>
... oh
<azonenberg>
derp
<azonenberg>
that would explain something
<rqou>
azonenberg: it sounds like you hare hitting the exact same things I was hitting as I was working on crbit :P
<azonenberg>
lol
<azonenberg>
Welp, the and array is still being annoying
<azonenberg>
And its 00:30
<azonenberg>
And i have to be up at around 0500 to fly to recon :p
<rqou>
the and array seemed pretty sane on the 32/64/256
<rqou>
it's the 128/384/512 one that's _lots_ of fun
<azonenberg>
yeah that isnt the issue
<azonenberg>
its just that i'm not parsing the bitfile right
<azonenberg>
trying to get a certain row of the and array and i'm getting a weird result
<rqou>
oooh i just realized why the 128/384/512 AND array "reversing" is grouped in groups of 3
<rqou>
PTA/B/C of each macrocell
<azonenberg>
Yeah that seems logical
<rqou>
i really need to draw a picture to explain wtf I'm talking about :P
<azonenberg>
it's showing as all 1s instead of 11111111111111011111111111111111111111111111111111111111111111111111111111111111
<azonenberg>
So i think i'm reading the wrong part of the bitstream
<azonenberg>
but i havent yet figured out what i'm doing wrong
<rqou>
azonenberg: should i make a coolrunner page on our (clusterf*ck of a) wiki?
<azonenberg>
There already is
<azonenberg>
oh wait
<azonenberg>
you mean on openfpga, not siliconpr0n
<azonenberg>
yeah there probably should
<rqou>
yeah there are also too many wikis :P
<azonenberg>
we need a major braindump of info
<rqou>
(i hate wikis, in case you can't tell)
<azonenberg>
and all of the coolrunner stuff on pr0n is specific to die RE
<azonenberg>
not much about the bitstream other than how it relates to the gates
<rqou>
the idea is great, but (tech/project) wikis always seem to turn into a giant pile of outdated braindumps
<rqou>
azonenberg: the sidebar/ToC on the wiki isn't automatic? I have to manually update it?
<azonenberg>
I dont know, i havent done much with the wiki :p