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<rqou>
taking the bus like a pleb and I notice that China's services are awful at "usability"
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<azonenberg>
rqou: so, lulzy idea
<azonenberg>
if you want a fun POC||GTFO artile
<azonenberg>
article*
<rqou>
what?
<azonenberg>
Make a coolrunner JIT :p
<rqou>
wtf?
<azonenberg>
modify my current emulator so it will translate the PLA AND/OR bits, and maybe the ZIA, from coolrunner native "opcodes" to shift register LUTs or similar
<azonenberg>
or LUTRAMs
<azonenberg>
dynamically build truth tables based on the bitstream
<rqou>
lool
<rqou>
goddammit azonenberg make xc2par work first :P
<azonenberg>
lol i wasnt going to actually *do* it, at least not soon
<azonenberg>
and i'm busy doing pcb deisgns for greenpak ptv characterization
<azonenberg>
The point was more, it would be hilarious if you could make a JIT that turned coolrunner bitfiles into something the fpga could execute more efficiently
<rqou>
that sounds totally possible
<azonenberg>
i know
<azonenberg>
i wanna do it, but not any time soon
<azonenberg>
gotta get the baseline unoptimized emulator working first
<rqou>
after doing par for the FPGA first :P
<azonenberg>
Hey, its not like my hands arent full...
<rqou>
anyways, I'm currently on the "pleb" bus again back into the city
<rqou>
going to take the cross-border bus tomorrow to HK to visit M-Labs
<azonenberg>
Say hi to sb0 for me
<azonenberg>
and whitequark if they're in the lab (idk about current location)
<rqou>
waiting for HK to finish their end of the Guangzhou-Shenzhen-Hong Kong high-speed rail
<rqou>
(should be done in 2018)
<azonenberg>
also, lol
<azonenberg>
after over a year of dev work on the greenpak tools
<azonenberg>
i am finally making a kicad footprint for the greenpak stqfn20
<rqou>
lool
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vQINg
<openfpga-github>
openfpga/master b08ddd9 Andrew Zonenberg: Initial version of gp4-stqfn20 board. Still needs final review prior to signoff.
<azonenberg>
Still have to do some tweaks, add silkscreen labels to the i2c header, etc
<azonenberg>
but basically ready to go
<rqou>
azonenberg: I just realized something
<rqou>
we should gpg-sign certain openfpga commits
<rqou>
e.g. the one I published xc2bit 0.0.1 from
<rqou>
we should start setting up a policy for how we're going to do this
<azonenberg_work>
io tiles on n/s/e/w of main array
<azonenberg_work>
Unknown logic, most likely config/jtag, in the corners
<azonenberg_work>
DCMs are the big cutouts just east/west of the centerline on the north side of the chip (with the big blue area)
<azonenberg_work>
Just below the right hand DCM are the multipliers and BRAMs
<azonenberg_work>
the BRAMs are the six dense arrays, two 9kbit arrays per BRAM (although in s3, unlke s6, the two arrays cannot be individually addressed)
<azonenberg_work>
immediately left of the BRAM is some addressing logic
<azonenberg_work>
then after that to the central spine are the multipliers and some routing logic driving the BRAM+MULT tile inputs (there's some shared douting and at the moment i dont fully understand that, i have to spend more time reading the datasheet)
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<balrog>
azonenberg_work: I see
<balrog>
hmm...
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