pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
<kbeckmann> hmm has anyone seen problems with using DFF and an INIT value? it seems to not work at all..
<kbeckmann> or rather, always initialize to 0
<kbeckmann> the problem i am trying to solve now is that i want that the OEN signal of IOBUF and TBUF to reset to 1 when in SDR mode. this is needed because when the bistream is loaded, the OEN signal will be 0, i.e. output tristate disabled, so you end up driving the signal even if you perhaps don't want to do that.
<kbeckmann> woa..! just did a quick test with the 10-bit serialized and it works on the tang nano. pretty cool. i wonder how fast it can go?
<kbeckmann> serializer*
<kbeckmann> hmm seems that OSER10 output fmax is 355. that's a bit of a shame. OSER16 goes up to 600MHz but is not available on all devices.
_whitelogger has joined #apicula
FabM has joined #apicula
FabM has quit [Ping timeout: 256 seconds]
FabM has joined #apicula
Conny40 has joined #apicula
Conny40 has quit [K-Lined]
<Lofty> kbeckmann: yes, we have seen those problems; the answer is that the flops initialise to their reset values and the INIT parameter is meaningless
<Lofty> So, DFF initialises to zero, but DFFS with an unused set initialises to one, AIUI
<pepijndevos_> They indeed initialize to the reset value. So DFFS inits to 1, DFFR inits to 0. DFF is basically DFFRE with reset and enable tied to gnd/vcc.
<kbeckmann> huh.. okay thanks for the insights
<kbeckmann> so if i don't care about being able to use the reset line, i can just instantiate a DFF or a DFFS depending on the init value i want then?
<Lofty> Correct
<Lofty> Although I'd consider just instantiating a $dff cell
<Lofty> Since ABC9 -dff might be added at some point
<Lofty> And that wants flops that initialise to zero
<kbeckmann> hm ok
<kbeckmann> what is a $dff cell? is that a yosys-specific thing? it would be cool to write code that can be synthesized with both the proprietary tool and yosys
<kbeckmann> for now i think i will use DFFS / DFFR instead
<daveshah> $dff will be converted to a generic dff by the verilog backend
<kbeckmann> okay
<kbeckmann> ah i see. so $dff is a verilog thing?
<daveshah> no it's a Yosys thing
<kbeckmann> aha ok
FabM has quit [Quit: Leaving]