pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
FabM has joined #apicula
<pepijndevos> I'm curious how other projects represent their clock routing?
<pepijndevos> In Apicula I have a grid, where each tile has a type that has an object that describes the bells and pips for that tile
<pepijndevos> But the clock stuff is kinda irregular and depends on the column and row the tile is on.
<pepijndevos> So if I store that in the general pips of each tile I'd have an explosion of different tile objects
<pepijndevos> So I'm kinda more leaning towards having a separate table of "global" pips... I just have to think that through a bit before I jump in and do it
<omnitechnomancer> I think trellis has some different stuff in the DB for "global" things
<pepijndevos> I'm now making a global alias table that maps to the pips that are already in the tiles. It will be a huge table, but pretty clean in terms of code I hope.
<pepijndevos> So like there is a pip already which maps e.g. CLK0 to A5 in the clock tile, which has neither. CLK0 actually refer to some IOB, so I just make an alias that connects everything up nicely, without messing with every tile.
<pepijndevos> So for the taps, I can alias which individual mux actually connects there on a global level