<pepijndevos>
My fuzzers are getting reeeeeaally slow for GW1N-9, and have not yet figured out a more efficient way.
<pepijndevos>
Step 1: sweep a dff across to see which center tile lights up to find the quadrants.
<pepijndevos>
(that's a 50+ runs already, maybe I should binary-search the boundaries?)
<pepijndevos>
For each 8 clocks, sweep a dff across to determine the boundaries of different branches
<pepijndevos>
that's another 8*50+ runs that I can't see how to really optimize.
<pepijndevos>
Because you can't directly route pips, you can't do the binary trick. You have to carefully set up the whole FPGA to coerce the vendor tools to use the clock you want.
<pepijndevos>
Hm, but if I binary search the boundaries it becomes sequential, whereas these 50+ runs I can run in parallel.
<omnitechnomancer>
I think my routing fuzzer for anlogic is extremely inefficient since it pretty much just attempts to connect each source to each destination in a tile and if bits come out records them
<omnitechnomancer>
but those tools let you actually give it something resembling routing pips
<pepijndevos>
At least I managed to fuzz the branch extends on GW1N-9 now...
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<trabucayre>
pepijndevos: my new trenz board is at home...
<pepijndevos>
yaaaay
<trabucayre>
Do you have an email that I send you the source of my bridge
<trabucayre>
I will try to don't brick them immediatly :)
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<pepijndevos>
my email is pepijndevos@gmail.com
<pepijndevos>
what do you mean with the bridge?
<trabucayre>
piece of verilog to do connect ftdi and flash
<pepijndevos>
oh, I already have it in migen for the LiteX target