pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
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<Lofty> Today in "Lofty's stupid LUT mapping experiments": trying to figure out if a function can be implemented in terms of two LUT4s connected to a hard mux
<pepijndevos_> oooh
<Lofty> ABC can't :P
<pepijndevos_> Not even if you feed it all combinations as seperate cells? haha
<omnitechnomancer> The simple case of the two LUT4's being a LUT5 with the mux or the more complicated case where teh two LUT4s can have different inputs?
<pepijndevos_> The latter, the normal wide lut is supported
<omnitechnomancer> I presume the normal wide lut is just figuring out if you can implement it with a LUT5 so not that hard
<omnitechnomancer> I assume yosys equivalence checking does not work with black boxes existing
<Lofty> omnitechnomancer: correct
<omnitechnomancer> Can black boxes be filled in by loading models for them?
<pepijndevos_> Welp... reading the nextpnr docs, and it just feels like a giant upfront all-or-nothing bunch of things to implement. Not sure where to start. I guess spend some time with the nexus code to see how stuff works in practice.
<omnitechnomancer> Yea it does have a bunch of things at all have to do before anything happens
<pepijndevos_> I guess I'll make a list of questions so I have to bother the expert only once hehe
<omnitechnomancer> :O
<Lofty> omnitechnomancer: thoughts?
<Lofty> Now that I've had a cup of coffee and a chance to lie down after burning a day's worth of spoons in four hours
<omnitechnomancer> Thoughts are that I need to sleep but it looks interesting from skimming and I shall read it in depth tomorrow
<omnitechnomancer> Have a good one
<pepijndevos_> spoons??
<pepijndevos_> ooooooh
<pepijndevos_> my gf once got me a spoon with a custom print. Now I want a bunch of spoons with various things that I exert energy on on a regular day.
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<Lofty> Morning omnitechnomancer
* Lofty also waves to notafile
<omnitechnomancer> Morning
<Lofty> omnitechnomancer: you're welcome in #prjmistral if you care
<Lofty> Welp.
<omnitechnomancer> Finished the first one, it was interesting, one question how are the primary inputs represented as nodes in the AIG? Do you just put in nodes with dummy LHS and RHS indices and rely on checking if the node is in the input list?
<Lofty> omnitechnomancer: yep, I was considering mentioning that, but decided it wasn't too relevant
<Lofty> AIGER also dedicates a constant zero driver as an input
<omnitechnomancer> Ah?
<Lofty> It's useful for logic manipulation
<Lofty> But for LUT mapping, it just adds confusion, I think
<Lofty> I'd probably implement it as LHS == RHS
<Lofty> Also, hope the Rust is readable
<Lofty> omnitechnomancer: ^
<Lofty> Since I'm probably going to sleep soonish
<omnitechnomancer> The Rust seems readable enough though in actual implementation could do with some new types to distinguish indices to the vector Vs the invert tagged indices in the AIG node
<omnitechnomancer> Though I suppose everything outside aug node uses just plain indices
<omnitechnomancer> Oh also I presume the depth vec is prefilled with some value to the same length as the nodes vec when populating the graph
<omnitechnomancer> Sleep well Lofty