pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
<omnitechnomancer> 3 centre tiles total or 3 left 3 right?
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<trabucayre> pepijndevos: I have an --spi option (draft) to access flash spi directly
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<pepijndevos> omnitechnomancer, three total
<pepijndevos> trabucayre, and uh, the gowin exFlash, or specifically the TEC0117 flash with a special bitstream?
<trabucayre> in fact, this option has don't care about device connected to FTDI :)
<trabucayre> you can use it to write a flash physically connected to an FT2232
<trabucayre> or with a bridge in the FPGA flash the external flash
<trabucayre> ./openFPGALoader --spi --interface 1 thing.bin
<trabucayre> (for interface 0 -> INTERFACE_A: ADBUSx, 1 -> INTERFACE_B: BDBUSx)
<pepijndevos> cool
<pepijndevos> bring your own bitstream :)
<pepijndevos> Is internal flash still bugged?
<trabucayre> I'm waiting for my new board...
<trabucayre> maybe today
<trabucayre> for VLD gowin support said it's a problem of VCC ramp. But since I've said "It's new, until now this board was perfectly working" no more message ...
<pepijndevos> oooohhh, maybe GW1NR-9 has 4 quadrants rather than 2 sides??
<pepijndevos> Yea actually seems like tiles 26-29 are clock roots
<pepijndevos> big oof
<pepijndevos> Also... since gowin confirmed that GW1NR-9 is just a GW1N-9 with a SiP SDRAM chip connected to one bank, maybe I should switch my fuzzing efforts to GW1N-9 to be able to fuzz that bank.
<pepijndevos> Yea that would speed things up a little bit, just have to confirm it keeps working...
<pepijndevos> GW1NR-9 has only 3 clock pins, so with 4 quadrants...
<pepijndevos> Although I'm also not using the 144 pin device for fuzzing which I should...
<omnitechnomancer> strange
<pepijndevos> ahhhhh it gets worse... it appears that 25 and 29 have A LOT of normal muxes configured, and then 25-29 have the spine muxes configured as before.
<pepijndevos> no sorry 26-29 have the spine muxes, 25 JUST has the "normal" muxes.
<pepijndevos> ooooh and also there are two spines it seems, at row 1 and row 19
<pepijndevos> WTFFFFF
<pepijndevos> tile 25 and 29 have exactly the same bits set btw... I'll look into decoding that later