pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
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<omnitechnomancer> The middle muxes might be getting signals into the clock tree?
<pepijndevos> omnitechnomancer, well yea, but there are two groups of muxes
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<pepijndevos> Apicula fuzzer now uses GW1N-9 instead of GW1NR-9. Same thing...
<pepijndevos> cue a dozen commits trying to fix CI
<trabucayre> pepijndevos: I've received my board
<trabucayre> and found an old, working, commit
<trabucayre> main difference: the old commit uses wrong MPSSE opcode :-/
<pepijndevos> wah
<pepijndevos> try with the wrong code? XD
<pepijndevos> Have you tried to bisect further?
<pepijndevos> (no idea what a MPSSE opcode does)
<pepijndevos> OH MY GOD... maybe I'm starting to figure out what the random routing bits are... and it makes me not want to support the 8th clock.
<pepijndevos> The routing muxes: {'C1': 'N220', 'A2': 'N210', 'N210': 'VSS', 'N220': 'VCC', 'S250': 'VSS', 'E270': 'VSS', 'B2': 'S250', 'D1': 'E270'}
<trabucayre> MPSSE are opcode used with ft2232 to send byte, bit
<trabucayre> a bisect is really difficult since most of the code has been modified
<pepijndevos> Ohhh I think there are these... dynamic clock muxes that allow you to switch between clock sources at runtime, maybe it's using one of those?
<pepijndevos> but then... pulled to VCC/VSS
<pepijndevos> ohnoooo
<pepijndevos> remember when I was like... ooh clear pattern lets hardcode. Patters breaks right after.
<pepijndevos> also, wtf, there are quadrants... except for two rows that break the pattern.
<pepijndevos> I guess designs with more than 6 clocks are not a top priority maybe hehe
<pepijndevos> (the reset/ce question also remains unanswered though)
<trabucayre> fucking shit! I've fixed MPSSE opcode in the old commit it's ever works...
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