pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
<omnitechnomancer> Does each clock tile have entirely different such mappings?
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<pepijndevos> omnitechnomancer, Well, the center clock tiles are kinda the same, but the taps and branches... they have the same fuses, but they connect to different things.
<omnitechnomancer> Ah, most unhelpful
<pepijndevos> What I settled on now is each tile just has its own R2C2_GBO0 etc. and I make a huge table of aliases that connect things up correctly.
<pepijndevos> (row 2 column 2 global buffer out 0)
<omnitechnomancer> ah
<pepijndevos> I finished that part yesterday. So now I have to verify I can use these aliases to actually find a path, and then actually add them to the DB, and update the nextpnr script to use them
<pepijndevos> or wait... maybe I still had a bug before bedtime haha
<pepijndevos> ah no I fixed that one
<pepijndevos> yaaay https://bpa.st/V6IQ
<pepijndevos> hmmm so clock fuzzer is a seperate thing from tiled fuzzer
<pepijndevos> I'm thinking I'll have tiled_fuzzer output {devices}_stage1.pickle and then have clock fuzzer read that and output stage2 and then have the makefile just cp the last one to <device>.pickle. That way make is happy and I can make multiple independent fuzzers.
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<pepijndevos> flucky plucky... potential problem:
<pepijndevos> the clock routing currently uses the same pin names as the general routing, but I don't think they actually correspond. I do not want to end up with general routing making a fake connection with the clock spine or something.
<pepijndevos> Probably add a rename pass...
<pepijndevos> I wrote half of that code already but deleted it. Why did I do that... silly me
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<pepijndevos> daveshah, ping
<pepijndevos> I added a bunch of pips and aliases to my generic script for clock routing, but nextpnr seems to ignore them.
<pepijndevos> Probably there is a "gap" somewhere that causes it to fail to route
<daveshah> Wire aliases are not actually supported and should be removed or implemented
<pepijndevos> w-wat...
<daveshah> Yeah sorry
<pepijndevos> lol
<daveshah> They were an idea from the early days of nextpnr that never really worked out
<pepijndevos> so this code has been wrong for a year or so
<daveshah> If the wires are only driveable one way, just replace them with pips
<pepijndevos> uh yea they are only one way
<pepijndevos> so... if I replace them with pips they show up in the output, and the packer has to deal with them, right?
<daveshah> Yes
<pepijndevos> I guess I could just name them FOO_ALIAS and ignore anything that matches ALIAS
<pepijndevos> daveshah, how is the loc of a pip used?
<pepijndevos> ITS WORKING?!?!
<pepijndevos> Well, the pnr part at least
<pepijndevos> I guess I'll do the packer tomorrow
<daveshah> It can be used by the router, router2 in particular, for bounding box checking
<daveshah> Great!
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