09:27 <trabucayre> pepijndevos: have you tested my fix ?

09:28 <pepijndevos> sorry no, I've been fighting spice this weekend

09:28 <pepijndevos> Is it merged yet, or do I need to checkout a special branch?

09:28 <trabucayre> special branch

09:29 <pepijndevos> okay lemme see

09:31 <trabucayre> All my tests prove openFPGALoader is not broken with other FPGAs/cable. My first goal for the week-end was to improve transaction... Finally, I have search how to integrate ADALM-2000 in sigrok

09:34 <pepijndevos> SRAM Flash: FAIL

09:34 <pepijndevos> 8124 0000

09:34 <pepijndevos> could just be secure bit?

09:35 <trabucayre> with : review_usb_transaction

09:35 <pepijndevos> it does actually appear to work

09:35 <pepijndevos> yea

09:35 <trabucayre> use -v and take log please

09:37 <pepijndevos> https://bpa.st/YCFQ

09:40 <trabucayre> Everything is good but status register seems not reloaded...

09:42 <trabucayre> could you provide your fs ?

09:42 <pepijndevos> yea how can I send it?

09:43 <trabucayre> I dont know :-/

09:43 <trabucayre> too big for a mail ?

09:51 <pepijndevos> It should work I think... worth a try

09:52 <trabucayre> gwe@trabucayre.com

10:01 <pepijndevos> on the way

10:02 <trabucayre> in the mail :)

10:06 <trabucayre> ok the bitstream is correctly written but the checksum is not updated ...

10:10 <trabucayre> Your bitstream take time to be loaded. I've added a delay before reading checksum and it's work

10:20 <omnitechnomancer> Can you query the doneness via JTAG?

10:28 <trabucayre> omnitechnomancer: yep. it's my idea too

13:19 <trabucayre> omnitechnomancer: it's weird, but if I poll in status register the bitstream fails to load...

13:19 <trabucayre> with a delay a bit longer it's works

13:19 <omnitechnomancer> weird

13:19 <pepijndevos> That sums up Gowin pretty well

13:19 <trabucayre> gowin programmer don't poll too. I need to check timestamp in wireshark dump for that

13:20 <trabucayre> pepijndevos: :)

13:20 <trabucayre> and of course this delay is not documented at all

13:22 <omnitechnomancer> who documents things

13:24 <trabucayre> omnitechnomancer: Yes I know... :-/

13:36 <trabucayre> pepijndevos: can you pull repo and test again? Now it must work.

14:13 <pepijndevos> CRC check: Success

14:22 <trabucayre> yess !

14:26 <pepijndevos> awesome

14:36 <trabucayre> I need to be sure openFPGALoader is not broken with others FPGAs and cables

14:38 <trabucayre> of course I'm open to able contribution :)

14:39 <trabucayre> your EBR is a good thing, thank to that I've fixed some limitations :)

15:10 <pepijndevos> EBR?

15:29 <trabucayre> UG290 p.46

15:30 <trabucayre> I seen this in another doc with size with and without this

15:30 <trabucayre> Extented Block Ram ? :)

15:31 <daveshah> embedded block ram iirc

15:31 <daveshah> that's what lattice use anyway

15:31 <pepijndevos> ahhh ok

15:46 <trabucayre> Am unable to find datasheet with bitstream size ...

15:46 <pepijndevos> yea I don't think you'll find that anywhere.

15:48 <trabucayre> I've read this this week

15:48 <trabucayre> after your problem with wrong CRC

15:48 <pepijndevos> oh? in that case I'm curious to read this document. Maybe it contains other useful bitstream information.

15:49 <trabucayre> I search :)

15:49 <trabucayre> but since I read crosslink datasheet, gowin, etc. I'm a bit lost :)

15:56 <trabucayre> UG290 p45

16:00 <pepijndevos> Table 6-1? So that

16:01 <pepijndevos> So that is the maximum number with BRAM right? It does not say the "minimum" size.

16:02 <trabucayre> yep 6-1

16:03 <trabucayre> awesome

16:03 <trabucayre> you need UG290-1.04

16:04 <trabucayre> WTF

16:17 <pepijndevos> ?

16:19 <trabucayre> I have ug290 1.04 and 2.0: first show configuration file size (with and without EBR), second shows max configuration file size

16:21 <pepijndevos> heeeeey

16:21 <pepijndevos> of course their site only has the latter, but my google drive has the former. or at least an old enough version

16:22 <trabucayre> funny :-/