pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
<trabucayre> it's weird. I'm trying to complete doc about bitstream: line starting with 0x10 is said as bootmode but when I play with loading_rate this area is changed according to the value used.
<pepijndevos> well, then the docs are probably wrong...
<pepijndevos> I'm assuming you're referring to https://github.com/YosysHQ/apicula/blob/master/doc/filestructure.md which is mostly done by daveshah, based on similarity to ECP5. So I think the meanings of the bytes are more educated guesses than hard science.
<pepijndevos> daveshah, placement does use the timing estimate, right? So if I write a better timing estimation function based on actual timing data, that might help?
<daveshah> yes but I wouldn't expect it to improve routeability significantly, only Fmax
<pepijndevos> But also... there are just 33% more LUTS per slice now, so routing is just that much denser.
<trabucayre> pepijndevos: not filestructure but commandstructure
<pepijndevos> trabucayre, ehhh, yea that's the one I mean
<trabucayre> ok :)
<daveshah> you can reduce beta in PlacerHeapCfg for a less dense placement
<pepijndevos> ohhh! I was about to say, I can just make it less dense again.
<pepijndevos> I'll try that.
<daveshah> (have a look at nexus arch.cc as an example)
<trabucayre> my problem (but it's may be delayed to a next round) is to find meaning of every values...
<pepijndevos> huraaaaaaa
<pepijndevos> beta did the trick
<pepijndevos> I'll do the better timing model anyway... I've already thought it out mostly.
<pepijndevos> and I guess the last item is fix CI?
<pepijndevos> welp... attosoc doesn't actually work. blinky is fine.
<pepijndevos> great when your reduced example is ok but the big huge thing is broken.
* pepijndevos screams
<pepijndevos> I think it's just my packer that's broken, not nextpnr.
<pepijndevos> but who knows....
<pepijndevos> yea the global clock wires aren't packed I think