pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
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<pepijndevos> Hmmmm, what if I write a python script that queries all the timing paths in nextpnr and then I can use that to wire a better prediction.
<daveshah> I think claire did something for ice40
<pepijndevos> Is there a python-accessible api for getting the delay between two ports, or something like that?
<daveshah> Not sure
<daveshah> No, looks like the routed delay functions aren't bound
<daveshah> In any event they need a routed net, not just two ports
<pepijndevos> Basically I want to tune the first number here to zero, right? https://github.com/YosysHQ/nextpnr/blob/master/common/router1.cc#L717
<pepijndevos> doesn't seem like it for some reason... made my delays very small and still positive numbers. Oh well, I'll come back to that later.
<pepijndevos> hokaaay constraints...
<pepijndevos> that's basically they key part right... https://github.com/YosysHQ/nextpnr/blob/master/nexus/pdc.cc#L349
<pepijndevos> wait... huh... in my current code I'm doing https://github.com/YosysHQ/apicula/blob/master/generic/blinky.v#L4
<pepijndevos> Basically just setting the BEL attribute on the IOB. I was thinking I'd just do the same but set the attribute from a constraint file
<pepijndevos> huuuhhh nice
<trabucayre> not too expensive
<pepijndevos> GW1N-UV4LQ144....
<pepijndevos> I guess I better get one to add it to Apicula
<pepijndevos> Is it me or is that a HUGE packages for such a small fpga?
<trabucayre> yep
<daveshah> that's why everyone does bga these days
<trabucayre> I'm unable to find this model
<pepijndevos> It's basically a GW1N-4. UV means it runs from 3.3V, and LQ144 is the package.
<trabucayre> ok
<trabucayre> order or not order that is the question :)
<pepijndevos> It seems a rather uninspired board, but gotta support it in Apicula :)))
<pepijndevos> If you just want a board to play with I think the Trenz board is in better in every way.
<trabucayre> it's more or less for openFPGALoader this time :)
<pepijndevos> I figured.
<pepijndevos> Well, I'll yell at you if it doesn't work haha
<pepijndevos> But should be compatible with the littlebee target, no? Unless they used yet another non-standard JTAG thing.
<trabucayre> ftdi I think
<trabucayre> In fact -4 is already supported
<trabucayre> I should rather play with my nexus
<pepijndevos> trabucayre, would this be suitable for programming a board without built in USB? https://www.seeedstudio.com/Sipeed-USB-JTAG-TTL-RISC-V-Debugger-p-2910.html
<trabucayre> pepijndevos: yep
<trabucayre> it's an ft2232
<pepijndevos> yayyy
<pepijndevos> I'm half thinking I'll design an FPGA board with a Fomu-like bootloader, but of course you need to get a bitstream on there somehow...
<trabucayre> you just need to take care about power, unlike digilent_hs2, this dongle is 3.3V only
<pepijndevos> And the digilent hs2?
<pepijndevos> Does Seeed sell any other fun toys I should get while I'm paying for shipping?
<pepijndevos> "Separate Vref drives JTAG/SPI signal voltages; Vref can be any voltage between 1.8V and 5V."
<pepijndevos> apparently...
<pepijndevos> But for like 10x the price that's a trade-off I'll gladly make
<trabucayre> I'm agree
<trabucayre> busblaster has buffer too
<trabucayre> but clearly more expensive
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