10:47 <pepijndevos> Hmmmm, what if I write a python script that queries all the timing paths in nextpnr and then I can use that to wire a better prediction.

10:54 <daveshah> I think claire did something for ice40

11:02 <pepijndevos> Is there a python-accessible api for getting the delay between two ports, or something like that?

11:04 <daveshah> Not sure

11:05 <daveshah> No, looks like the routed delay functions aren't bound

11:05 <daveshah> In any event they need a routed net, not just two ports

11:15 <pepijndevos> Basically I want to tune the first number here to zero, right? https://github.com/YosysHQ/nextpnr/blob/master/common/router1.cc#L717

11:23 <pepijndevos> doesn't seem like it for some reason... made my delays very small and still positive numbers. Oh well, I'll come back to that later.

12:14 <pepijndevos> hokaaay constraints...

12:19 <pepijndevos> that's basically they key part right... https://github.com/YosysHQ/nextpnr/blob/master/nexus/pdc.cc#L349

12:22 <pepijndevos> wait... huh... in my current code I'm doing https://github.com/YosysHQ/apicula/blob/master/generic/blinky.v#L4

12:23 <pepijndevos> Basically just setting the BEL attribute on the IOB. I was thinking I'd just do the same but set the attribute from a constraint file

12:24 <pepijndevos> ohhh here is where the conversion happens https://github.com/YosysHQ/nextpnr/blob/ca08add9c90b14e4fb8d63ccb4f475dccd598d66/nexus/pack.cc#L622

15:31 <trabucayre> pepijndevos: https://www.seeedstudio.com/Gowin-RUNBER-Development-Board-p-4779.html?utm_source=mailchimp&utm_medium=edm&utm_campaign=bazaar_1210

15:35 <pepijndevos> huuuhhh nice

15:35 <trabucayre> not too expensive

15:36 <pepijndevos> GW1N-UV4LQ144....

15:37 <pepijndevos> I guess I better get one to add it to Apicula

15:38 <pepijndevos> Is it me or is that a HUGE packages for such a small fpga?

15:38 <trabucayre> yep

15:38 <daveshah> that's why everyone does bga these days

15:38 <trabucayre> I'm unable to find this model

15:39 <pepijndevos> It's basically a GW1N-4. UV means it runs from 3.3V, and LQ144 is the package.

15:40 <trabucayre> ok

15:40 <trabucayre> order or not order that is the question :)

15:41 <pepijndevos> It seems a rather uninspired board, but gotta support it in Apicula :)))

15:42 <pepijndevos> If you just want a board to play with I think the Trenz board is in better in every way.

15:42 <trabucayre> it's more or less for openFPGALoader this time :)

15:43 <pepijndevos> I figured.

15:43 <pepijndevos> Well, I'll yell at you if it doesn't work haha

15:44 <pepijndevos> But should be compatible with the littlebee target, no? Unless they used yet another non-standard JTAG thing.

15:44 <trabucayre> ftdi I think

15:44 <trabucayre> In fact -4 is already supported

15:54 <trabucayre> I should rather play with my nexus

16:02 <pepijndevos> trabucayre, would this be suitable for programming a board without built in USB? https://www.seeedstudio.com/Sipeed-USB-JTAG-TTL-RISC-V-Debugger-p-2910.html

17:09 <trabucayre> pepijndevos: yep

17:09 <trabucayre> it's an ft2232

17:10 <pepijndevos> yayyy

17:10 <pepijndevos> I'm half thinking I'll design an FPGA board with a Fomu-like bootloader, but of course you need to get a bitstream on there somehow...

17:11 <trabucayre> you just need to take care about power, unlike digilent_hs2, this dongle is 3.3V only

17:19 <pepijndevos> And the digilent hs2?

17:20 <pepijndevos> Does Seeed sell any other fun toys I should get while I'm paying for shipping?

17:22 <pepijndevos> "Separate Vref drives JTAG/SPI signal voltages; Vref can be any voltage between 1.8V and 5V."

17:22 <pepijndevos> apparently...

17:22 <pepijndevos> But for like 10x the price that's a trade-off I'll gladly make

17:51 <trabucayre> I'm agree

17:51 <trabucayre> busblaster has buffer too

17:51 <trabucayre> but clearly more expensive