pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
<omnitechnomancer> if you find valgrind too slow and aren't after uninit memory try -fsanitize=address
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<omnitechnomancer> problems going away when you shuffle things is usually a sign of out of bounds writes that have happened to hit benign spots now
<pepijndevos> ohhhh I'm actually getting to the bits where I need to express the constraints on the slices, exciting stuff :))
<pepijndevos> ERROR: Found two arcs with same sink wire R5C23_CE1: cpu.latched_rd[2]_LUT2_I0_F_LUT3_I0_F_LUT3_I1_F (3) vs cpu.latched_rd[2]_LUT2_I1_I0_LUT2_I0_F_LUT2_I1_F (3)
<pepijndevos> there is a constraint that makes all the clocks the same per tile, but not for enables and resets yet :)))
<omnitechnomancer> \o/
<pepijndevos> And Gowin actually has more fine-grained clock/reset/enable than per tile, so yay
<omnitechnomancer> can you have two of each per tile?
<pepijndevos> Each tile has for pairs that each have their own
<pepijndevos> *four
<omnitechnomancer> ah
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<pepijndevos> blegh
<pepijndevos> routing makes it a long way and then
<pepijndevos> Warning: Failed to find a route for arc 0 of net cpu.mem_wdata[0]_DFFE_D_Q[7].
<pepijndevos> ERROR: Routing design failed.
<pepijndevos> let's try a simpler design...
<pepijndevos> Weird that it'd fail on some completely normal-looking DFF after routing a few thousand others
<pepijndevos> Ah, I think some routing is missing from the IOB to the fabric