07:40 <pepijndevos> gatecat, why is it unsound?

07:42 <pepijndevos> Each tile has 4 configurable logic slices, which share their reset and enable. So cls is the slice, and if the dff has a non-null ce, then if there is another dff in the same cls it has to match

07:42 <gatecat> Imagine if it first finds a ff with no ce, so it stays at nullptr, then an ff with ce which it thinks can be placed in the same tile but actually that's invalid

07:43 <gatecat> the problem is that it allows a dff with null ce and a dff with nonnull ce to be placed together

07:44 <pepijndevos> hm... I *think* that's what I fixed with the check for the mode, but... not all parts of my code distinguish between dff and dff because they are the same in the bitstream

07:44 <pepijndevos> *dff and dffe

07:44 <pepijndevos> so uh... if dff and dffe have the same mode yea it'd break... I need to check that

07:44 <pepijndevos> good catch

07:50 <pepijndevos> In yosys they are different types. So DFFE and DFF should never be in the same cls based on their type

07:51 <pepijndevos> Yea I only get rid of the E at the very end https://github.com/YosysHQ/apicula/blob/master/apycula/gowin_pack.py#L51

08:02 <gatecat> ah that's fine then

08:10 <pepijndevos> Thanks a lot for thinking along though :) It's a very tricky problem.

08:10 <pepijndevos> I think my next step will be to verify the correctness of the unpacker with the vendor bitstream of the broken example.

08:11 <pepijndevos> Looks suspicious.