pepijndevos changed the topic of #apicula to: Project Apicula: bitstream documentation and tooling for Gowin FPGAs https://github.com/YosysHQ/apicula -- logs https://freenode.irclog.whitequark.org/apicula
<omnitechnomancer> Can you have a db version that omits the edge folded wires just to check it's not that?
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<pepijndevos> Possible
<pepijndevos> But kinda tricky because it depends on the position and length and you still need to be able to reach the edge
<trabucayre> It's seems to be a "blind debug" no ?
<trabucayre> pff the nextpnr master branch throws an error :(
<trabucayre> terminate called after throwing an instance of 'nextpnr_gowin::assertion_failure' what(): Assertion failure: pips.count(name) == 0 (/home/gwe/misc/icestick/nextpnr/gowin/arch.cc:74)
<trabucayre> if I display name I have R1C1_N240_CLK0 twice
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