omnitechnomancer has quit [Ping timeout: 244 seconds]
kprasadvnsi[m] has quit [Ping timeout: 268 seconds]
omnitechnomancer has joined #apicula
omnitechnomancer has quit [Ping timeout: 265 seconds]
kprasadvnsi[m] has joined #apicula
<pepijndevos>
maybe?
wiizzard has joined #apicula
notafile has joined #apicula
omnitechnomancer has joined #apicula
<trabucayre>
pepijndevos: need to validate crc and everything will be working
<pepijndevos>
wow amazing
<trabucayre>
PR done !
<trabucayre>
maybe test before apply :-)
<trabucayre>
I'm not really happy to update hdr in write bitstream, but it's to avoid many numpy conversions...
<pepijndevos>
Yea, the last 3 days I did basically nothing but chores and playing in the snow. Tomorrow more chores and then maybe fiiinally do some Apicula.
<pepijndevos>
At least merge the PR and test your example
<pepijndevos>
Coming week I'm only working two days, so should be more opportunity to really dive into Apicula later that week.
<trabucayre>
ok :)
<trabucayre>
don't worry :)
<pepijndevos>
I only worry... a bit. Just want to have... *some* progress this month.
<trabucayre>
Understandable
<trabucayre>
:
<trabucayre>
:)
<trabucayre>
My dream now is to search for the bug... But no idea where to start... :-/
<pepijndevos>
That makes two of us...
<pepijndevos>
Maybe I should livestream my struggle to give an idea how much it's just cluelessly messing around
<pepijndevos>
My best guess is I extracted some clock route from the DB that isn't actually there
<trabucayre>
In fact when I said "no idea" it's because FPGA reverse is a bit mysterious for me. debugging a driver, an application or reversing some parts of a bitstream is quite easy but this type of debug...