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<trabucayre>
omnitechnomancer: to use an SPI device directly from a userspace app spidev is fine
<trabucayre>
but for a driver you have to use the SPI structure
<omnitechnomancer>
of course if you are writing a kernel driver using the spi subsystem is the way to go
<trabucayre>
for gowin, if it used in SSPI mode it make sense to contribute a driver :)
<pepijndevos>
wow I missed a lot going on here
<pepijndevos>
hi disasm
<pepijndevos>
What does it mean for the kernel to support an fpga driver?? Does that mean you just get to yeet a bitstream at /dev/fpga1?
<trabucayre>
pepijndevos: more or less yes
<pepijndevos>
Is it basically just kernel space openFPGALoader? What's the point?
<trabucayre>
openFPGALoader is usefull to deal with FPGA through usb-jtag or when your host is unable to communicate using SPI or JTAG
<trabucayre>
for a embedded board where it's possible to have a real SPI (or a parallel bus) it make sense to use kernel's fpga infra
<trabucayre>
for zynq and socfpga it's the usual way
<pepijndevos>
hm okay so if I want to do my raspi slave spi board it'd be useful to have a kernel driver
<trabucayre>
It's not mandatory but yes :)
<trabucayre>
I'm interested to write this driver :)
<trabucayre>
SSPI and/or CPU mode
<pepijndevos>
I'm interested to make the pcb, so sounds like a good combi
<trabucayre>
maybe a coworking with disasm[m] ?
<trabucayre>
his board seems good to that
<pepijndevos>
He shipped me one of his boards, but it'll be a while before apicula supports the GW1N-2C or whatever it is that has the ARM core
<trabucayre>
one important thing: MODE[0:2] must have jumper :)
<trabucayre>
and all pins must be availables :)
<pepijndevos>
I'm thinking more in the direction of a Pi Zero shield that is specifically made for slave mode programming by the Pi. All the Pi GPIO connected to the FPGA and the remainder to PMOD... or something else
<disasm[m]>
<pepijndevos "What does it mean for the kernel"> No idea why linux has these drivers, maybe for convenience. I think that userspace SPI is enough, at least for ice40
<pepijndevos>
The main use would be automated testing of Apicula to avoid regressions. But might be useful for other things too
<trabucayre>
a PI 40pins is good :)
<trabucayre>
disasm[m]: these structure is primarly for zynq & socfpga
<trabucayre>
but boards like armadeus apf has both CPU and FPGA
<disasm[m]>
Also I don't see why we need SSPI for programming the FPGA when we have JTAG enabled all the time
<disasm[m]>
For GW1N-2C JTAG is also needed to debug the MCU inside, so one has to use JTAG anyway
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<trabucayre>
SPI is most commonly available than a jtag master :)
<pepijndevos>
Yea this SSPI discussion originated in wondering how a Raspi could program an fpga. It does not have hardware JTAG so you'd have to bitbang it, or have a bridge chip... or just load the bistream in SSPI mode
<trabucayre>
and the FPGA may be used as accelerator (without MCU) or frontend
<disasm[m]>
Ah, I see
<disasm[m]>
Ugh, I need to assemble yet another board. Still waiting for parts.
<pepijndevos>
Me on the other hand, am waiting for boards stuck in customs...
<disasm[m]>
I can make a special SSPI-enabled version :D Nothing that bodge wire can't solve
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<disasm[m]>
Hmm, it's already SSPI-enabled as MODE[2] is tied to ground
<trabucayre>
there is 3 MODE pins
<trabucayre>
(maybe it's not true for all device :)
<disasm[m]>
Maaaybe
<pepijndevos>
Yea some packages only expose a subset which is really annoying
<pepijndevos>
kinda bricked my tang nano that way once. If you get messy with dual-mode pins you can get into situations where you need to set some pins that the package or the board don't expose
<trabucayre>
pepijndevos: arggg
<disasm[m]>
Given "As the selection pin of GowinCONFIG modes, MODE is an input pin that has internal weak pull-up." I guess on my board MODE is 011 which is neither SSPI nor MSPI
<pepijndevos>
I think the default is like dual or auto or something right
<trabucayre>
and 111 ?
<disasm[m]>
Hmm, "As the number of pins for each package is different, some MODE pins are not all bonded out, and the unbound MODE pins are grounded by default."
<disasm[m]>
Anyway, the result is the same :(
<disasm[m]>
Yeah, it's auto boot from internal flash
<trabucayre>
111 -> CPU Mode
<pepijndevos>
Right so you need a package with all mode pins available...
<trabucayre>
the one in tech0017 has 2, runber 2
<trabucayre>
both have MODE0 & MODE1
<pepijndevos>
hmmm
ZirconiumX is now known as Lofty
<omnitechnomancer>
<pepijndevos "What does it mean for the kernel"> the linux kernel has a framework for loading images into FPGAs because this comes up a reasonable amount in various things linux runs on
<omnitechnomancer>
<disasm[m] "No idea why linux has these driv"> when you have to get a blob into the fpga as part of the boot process it comes in handy, or for when some peripherals are behind it (though the boot process case more likely makes the bootloader load the initial config)
<trabucayre>
omnitechnomancer: I prefer contributing to linux
<trabucayre>
uboot is a bit "strange" :)
<omnitechnomancer>
it is a bit strange
<trabucayre>
denx is sometime huggly
<trabucayre>
I think seriouly to move to barebox
<trabucayre>
I use it with my de0nanoSoc
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