<kbeckmann>
what do you call the artifact that nextpnr-gowin creates in json format? "bitstream in json format"?
<kbeckmann>
i just got my nmigen integration working now where nmigen writes yosys .il, which is processed by yosys which writes a json netlist, that is then processed by nextpnr-gowin and finally packed by gowin_pack.
<kbeckmann>
(and it works with both the proprietary toolchain and apicula/yosys/nextpnr)
<trabucayre>
connectors is empty ... :)
<kbeckmann>
hm yeah. i wonder if there is anything i can put there since all of the pins are used by something iirc
<trabucayre>
when lcd is not used all pins are free to use
<trabucayre>
NMIGEN_ENV_Apicula is necessary ? my understand is a shell to fill env vars no ?
<kbeckmann>
good point
<kbeckmann>
no you don't have to set it
<trabucayre>
is it necessary to mention this in description ?
<kbeckmann>
copy paste boiler plate :)
<kbeckmann>
i can remove it if it doesn't really clarify anything
<trabucayre>
* ``{{name}}.json``: Synthesized RTL. <- s/json/il/g no ?
<kbeckmann>
yeah i suppose. i based that from the ecp5 platform file. but you're right, there is no RTL here per se.
<trabucayre>
sorry mistake
<trabucayre>
kbeckmann: Warning: Invalid constraint: # Automatically generated by nMigen 0.3.dev255+g7a4c03e. Do not edit.
<kbeckmann>
ah it seems comments are parsed as // in nextpnr/gowin/arch.cc
<kbeckmann>
weird. i am able to run my lcd demo, but blinky seems to not blink anymore for me.
<kbeckmann>
it seems kinda random. sometimes it blinks once and then gets stuck at either high or low. wonder what i messed up this time.
<trabucayre>
pff I have again problem with ch552 ...
<kbeckmann>
hm ok so my issue goes away if i tell yosys to read the generated verilog instead of the generated ilang from nmigen.
<kbeckmann>
wow. i saved the json output files and diffed them. they differ a lot.
<trabucayre>
nmigen works for me
<kbeckmann>
okay. i wonder what's going on on my end then.
<trabucayre>
hard to say :)
<kbeckmann>
yeah.. think i should make a tiny design and work my way up from there.
<kbeckmann>
what i see is that my relatively complex lcd demo works, but nmigen's built in blinky does not. it behaves differently each time i build it. howver, if i tell yosys to read the verilog output, it works 100% of the time.
<kbeckmann>
also, if i diff the json output from yosys when it reads .v or .il, it differs a lot. can't really say what it differ (so many differences that i can't say really what's going on)
<trabucayre>
and if you use .il it's the same ?
<trabucayre>
I retry many time from scratch and it's okay each time
<trabucayre>
(with // instead of # )
<trabucayre>
maybe a regression before commit I use and HEAD
<kbeckmann>
yeah possibly. i just rebuilt yosys.
<trabucayre>
no I talk about nmigen :)
<kbeckmann>
ah.
<trabucayre>
and I use pip3 for apycula
<trabucayre>
nmigen HEAD work with my tang_nano
<trabucayre>
why there is no more sdc file ?
<kbeckmann>
because it is not used by nextpnr yet
<kbeckmann>
it gets generated for the gowin toolchain if you choose to use that though
<trabucayre>
ok
<kbeckmann>
the cause of the problem is the POR generator which i more or less copied from the ice40 code. removing it fixes the issues for me.
<kbeckmann>
i'm still a bit confused as to why it caused an issue at all though, as it is basically just a counter which asserts a global reset signal and deasserts it when it has finished counting. unless there's a bug in that code..
<trabucayre>
and why it's okay with my computer
<trabucayre>
maybe different release of yosys, nextpnr and apicula...
<kbeckmann>
yeah, would be nice to go to the bottom of this. but not today for me.