#asahi-re on 2021-01-21 — irc logs at freenode.irclog.whitequark.org

2021-01-11 09:52 marcan changed the topic of #asahi-re to: Asahi Linux: porting Linux to Apple Silicon macs | Hardware / boot process / firmware interface reverse engineering | WARNING: this channel (only) may contain binary reverse engineering discussion | RE policy: https://alx.sh/re (MANDATORY READ) | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-re

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13:26 <davidrysk[m]> I’m really curious what’s really up with nGnRE. Does Apple just never use it in their drivers? They do provide a way to map that memory

13:26 <davidrysk[m]> Someone did say that they do “fabric config”

13:29 <opticron> oh...I guess if the interconnects are smart enough they could just do it there

13:30 <davidrysk[m]> e.g. what registers are used to configure that

13:30 <opticron> I'm sure it's in the device tree somewhere

13:30 <opticron> the devices themselves, not the regs

13:31 <opticron> maybe they use standard ARM CCN?

13:32 <opticron> is the Apple device tree on the wiki somewhere?

13:40 <never_released> davidrysk[m]: even more complex than this

13:40 <never_released> will explain later

13:40 <never_released> the workaround is broken, as Apple actually uses nGnRE for some _other_ things

13:41 <davidrysk[m]> The big question: is this specific nGnRE breakage intentional?

13:41 <davidrysk[m]> (Or the design that leads to this behavior)

13:42 <never_released> it isn't broken

13:42 <never_released> well

13:43 <never_released> it's behaving as designed.

13:43 <never_released> basically: use nGnRnE and everything on SoC works, but PCIe MMIO gets blackholed, use nGnRE and PCIe works but everything on SoC gets to nowhere

14:14 <yrlf> never_released: that is batshit insane

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14:44 <Shiz> wow

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22:35 <davidrysk[m]> never_released: btw I am very curious as to how Apple's "fabric" works, especially considering this testing: https://lemire.me/blog/2021/01/06/memory-access-on-the-apple-m1-processor/

22:35 <davidrysk[m]> (also, Apple has never told us how much shared memory is present inside the SoC)

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