18:42 <marex> sravn: drm/panel: simple: add panel-dpi support ... thank you for that, its just what I need now

19:23 <sravn> marex: You are welcome. Let me know if you hit any problems as it is not tested

19:24 <sravn> marex: I am a bit worried that we need to specify so many delays for diverse panels and this general approach do not allow it (yet)

20:02 <marex> sravn: I will just let others test it :)

20:03 <marex> sravn: if there is a report, I will keep you posted

21:25 <pdp7> Hello, I am talking to a company with an upcoming RISC-V SoC with Vivante GC8000L and it will work with etnaviv

21:26 <pdp7> Any tips on how one could start testing compatibility?

21:26 <pdp7> The developer with the test board has mainline kernel booting on it. I figure entaviv drm driver needs to be enabled and the correct compatible node added to device tree? And then configure mesa?

21:27 <pdp7> This SoC will have performance similar to ARM A73 so exciting if GPU works with open drivers

21:29 <austriancoder> pdp7: hi.. risc-v nice! Yup add the needed etnaviv device tree stuff an the kernel should be ready. Is there already a KMS driver? Etnaviv is a renderonly GPU so it is more fun with KMS.

21:30 <pdp7> Ah ok. I'm not sure about that. Currently they used SDK from Vivante but I'm hoping that can be switched to upstream support. I'll ask about KMS. Thanks

21:31 <austriancoder> pdp7: here is the link to the device tree binding: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/gpu/vivante,gc.yaml?h=v5.10-rc5

21:32 <pdp7> Thanks

21:32 <austriancoder> getting that working is a good first step

21:33 <pdp7> Ideally, we will be using this in a new RISC-V BeagleBone and finally not be burdened with PowerVR anymore

21:34 <austriancoder> nice.. tbo I never had any contact with risc-v so I am really excited

21:56 <pdp7> every other RISC-V SoC that I know of is using Imagination so I am really happy this one company decided to use Vivante

21:58 <pdp7> sadly, the NXP RISC-V test SoC that with I.MX style peripherals (announced last december) is not happening but there are many chips that will be coming out in 2021 from chinese vendors including this one with Vivante GC8000L

21:59 <pdp7> all the vendors I've talked have promised english datasheets but we shall see if they really deliver on that

21:59 <mntmn> ohai pdp7

21:59 <pdp7> hi!

22:00 <pdp7> mntmn: I've had you in mind when talking to risc-v soc vendors.... some of the chips planned are too expensive for a beaglebone priced board but might make sense for the laptop :)

22:00 <mntmn> pdp7: exciting!

22:00 <pdp7> there will be a lot of exciting announcements in 2021

22:01 <mntmn> pdp7: oh, core-v apu is not happening?

22:01 <pdp7> this one with Vavante GC8000L will be similar performance to Cortex A73 and can have up to 16 cores so that could make a nice reform module :)

22:01 <mntmn> :O

22:08 <pdp7> yeah, the core-v apu is not happening as announced

22:08 <pdp7> NXP decided not to do it this year

22:09 <pdp7> OpenHW is still working on the core (CVA64) but there is no SoC planned currently. It is just FPGA for now. OpenHW is taping out a microcontroller with NXP based on ZeroRISCY from ETH Zurich

22:10 <pdp7> which makes sense to start small, just not helpful for Linux. But there will be several exciting options from China in 2021.... it just won't be an iMX design which is bit of a bummer

22:10 <pdp7> maybe when life (and budgets?) gets back to normal NXP will get more aggressive agai

22:11 <pdp7> *again and tape out a test SoC

22:12 <pdp7> oops, its the CV6A https://github.com/openhwgroup/cva6 as in Core-V 6 stage pipeline Ariane (from ETH Zurich)... not very catchy :D

22:42 <mntmn> pdp7: ok, thanks for the update!