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<Zarutian_HTC> folks here have dealt with various designs of MCUs, no?
<Zarutian_HTC> anyone come across one with memory address space mapped io and bankswitched memory address space with the following twist
<Zarutian_HTC> one bank is where the control registers for the bank switching is located. One with two profiles that you can switch between as active
<Zarutian_HTC> one profile gets switched to automatically on interrupt
<Zarutian_HTC> anyone seen such a setup?
<MrMobius> how do you switch banks if you write the register that deselects the bank? wont you be stuck then?
<Zarutian_HTC> allows for process seperation without using page tables
<Zarutian_HTC> more than one bank slot in the address space
<Zarutian_HTC> and the returnFromInterrupt switches back between the two profiles
<MrMobius> so at least one fixed bank?
<Zarutian_HTC> no fixed bank but a power-on-defaults setup in the active profile
<Zarutian_HTC> basically nearly fully virtualizable if one of the 'bank' causes interrupt on access
<Zarutian_HTC> saw this design in some old 6502 computer used for industrial automation
<Zarutian_HTC> the out pin from the 6502 for external interrupts enable was used as the bank profile active selector
<MrMobius> neat
<Zarutian_HTC> the thing had more memory than fit into the limited 64K address space, but it did implement preemptive noncooperative task switching
<MrMobius> ya bank switching is pretty common on 6502 stuff
<Zarutian_HTC> and this meant that many tasks could be running but each thinking it was the only thing running
<MrMobius> ah I see what you mean. ot just a bank for interrupts but a number of banks and you go to the next one every time the interrupt fires?
<Zarutian_HTC> yebb, common but not in this way where the banks selection setup, the profiles, was in one bank that could be denied to other tasks
<Zarutian_HTC> a more concrete example:
<Zarutian_HTC> the 64K address space is split up into 16 bank slots
<Zarutian_HTC> each slot can select between 256 banks
<Zarutian_HTC> one of these banks provides access to two 16 bank selection profiles
<Zarutian_HTC> that is the registers saying which bank slot has which bank in it
<Zarutian_HTC> one of them is always active, which one depends on the external interrupt enable pin from the 6502
<Zarutian_HTC> the first profile that is active at power-on has default setup
<Zarutian_HTC> meaning that the banks with the rom, the io, and the bank selection profiles are accessible
<MrMobius> what about the other 3 banks? 16k is kind of limited for code+data. one code bank and at least two data banks is nice
<Zarutian_HTC> 255 banks each 4K in size
<Zarutian_HTC> but there is only 16 bank slots per profile.
<Zarutian_HTC> meaning each can select one bank from the the 255 available
<MrMobius> so then how does it change the slots while it's running?
<Zarutian_HTC> by writing into either of the 'profile' in the bank that keeps the two profiles
<Zarutian_HTC> it switches from profile 0 to 1 via rfi instr (the external interrupt enable) and back again when an interrupt occurs
<MrMobius> so it cant switch the slot assignment until the interrupt fires again?
<Zarutian_HTC> this memory bank unit made it possible to do something akin to kernel/user mode and virtualization with very little hardware
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<Zarutian_HTC> it can only change the slot assignments iff the bank where the two profiles is mapped in
<Zarutian_HTC> so, yesþ
<Zarutian_HTC> s/þ/./
<Zarutian_HTC> one of the selectable banks just caused interrupt when accessed
<Zarutian_HTC> so it was fully virtualizable
<Zarutian_HTC> I was pretty astonished how little hardware wise it needed for its implementation
<Zarutian_HTC> but you could wedge yourself into a corner if neither of the profiles had the profiles bank mapped
<Zarutian_HTC> how was the power on defaults implemented? both profiles lived in a small sram whose address line also fed into a small rom
<Zarutian_HTC> the rom output got xored into the data lines of the sram
<Zarutian_HTC> so when the sram was zeroed on power up you got the default values
<MrMobius> so guessing the clock speed was kind of low
<Zarutian_HTC> when writen to the sram actually contained the default value xored with the intended value
<Zarutian_HTC> around one megahertz or so
<MrMobius> probably enough depending on what youre doing
<MrMobius> delays start stacking up really quickly so putting a XOR or anything else drops your max clock really quickly
<Zarutian_HTC> it was a fast enough xor chip
<MrMobius> right you can add all kinds of delays if youre running at 1mhz
<Zarutian_HTC> this thing was designed and built in the 1980's or so for industrial machine control applications
<Zarutian_HTC> I just found it neat that you could do task/process seperation without the big or complicated mmu
<lispmacs[work]> Zarutian_HTC: what is the model of this system?
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