<d1b2>
<konsgn[no-Mic]> what about @Sprite_tm 's solution on the superconf badge. add a 2x1 pin header to where the slot in the idf connector is... or wait... are both slots pointing in?
<d1b2>
<konsgn[no-Mic]> oooph yea, they're both pointing in, scratch that last comment.
<d1b2>
<konsgn[no-Mic]> could also add the mounting holes to make it clear which way it orients.
<d1b2>
<thomasflummer> Are port A and B that different, so it's a problem if it's rotated?
<d1b2>
<konsgn[no-Mic]> One more comment, you could replace the electrolytic with a bank of ceramics. re: similarities: pretty sure they are exactly the same.
<d1b2>
<thomasflummer> well... I guess the software side might not be...
<d1b2>
<konsgn[no-Mic]> it would just make it tricky if planning the functional connections since he has non-symetrical functional groupings.
<d1b2>
<konsgn[no-Mic]> also, dual tvs for the data lines is redundant, and it would be harder to figure out which is bad if you have 2, only one tvs can blow at a time, so it makes sense to have just one package.
<d1b2>
<konsgn[no-Mic]> ... sorry last note: perhaps it would be cleaner having both ports sticking out the bottom. that way you have no cabling going over the glasgow.
<d1b2>
<TomKeddie> You could link two of the unused pins and use the software to test the orientation and adapt accordingly. Seems like overkill though, it's a test tool, some level of skill can be expected.
<d1b2>
<rwhitby> Ports are different, one needs to be 5V, one needs to be 3V. Swapping them will fry chips.
<d1b2>
<rwhitby> Looks like I'm getting conflicting input on TVS. @electronic_eel recommended one for each connector.
<d1b2>
<rwhitby> The software is going to bring up Port A at 3.3V and check for FUSB302 access before then going to 5V. It can then report failure to find FUSB302 to the user before blowing up any chips.
<d1b2>
<rwhitby> Too late for both ports out the bottom. The top port is hardly ever used (only use case at the moment is if you have a Luna board as well), so having the cable over the top of Glasgow is not a problem.
<d1b2>
<rwhitby> What's the pro's/con's for single electrolytic vs bank of ceramics? Again, @electronic_eel recommended elec.
<d1b2>
<rwhitby> Squaring off the top edge is how we're going to indicate orientation. There's also large A and B port indicators which will match the case marking on Glasgow.
<d1b2>
<rwhitby> (thanks everyone for your inputs)
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<d1b2>
<konsgn[no-Mic]> Now I'm curious why 2 tvs were recommended. Re: electrolytic vs ceramic, electrolytic is great for bulk capacitance, but is tall /bulky. if you use a bunch of ceramics/ maybe a tantalum or 2 you can shrink the height of the board. ceramics have no polarity, but do be mindfull of the voltage bias derating.
<d1b2>
<rwhitby> board height isn't a concern here
<d1b2>
<rwhitby> I'll wait for @electronic_eel to comment on the pro's/con's.
<d1b2>
<rwhitby> this particular cap is intended to cover the surge on 5V from glasgow when this board is configured as DFP and is supplying VBUS to something that is plugged in.
<d1b2>
<DX-MON> in this case, konsgn, the electrolytic is picked because it is bulk capacitance.. to get the same in ceramics.. is going to take a ton more board space and possibly not even quite cover the use case in question
<d1b2>
<DX-MON> more caps in parallel does not always the same effect as one big one make
<d1b2>
<DX-MON> you would need 12 10uF caps rated to 16V to get the same effect.. which means 12 0603 or larger packages to fit
<d1b2>
<DX-MON> and that's only /possibly/ the same effect
<d1b2>
<DX-MON> and not taking into account DC derating properly
<d1b2>
<rwhitby> Note that a key design goal for this board is jlcpcb assembly. So any part added needs to be available there.
<d1b2>
<DX-MON> that's a cute tiny firecracker.. I mean tantalum
<d1b2>
<DX-MON> (I have nothing against tantalum caps.. they just really dislike having their positive terminal taken below their negative voltage-wise, even for a teeny moment)
<d1b2>
<DX-MON> (they are also a conflict metal.. which is a shame given how useful they are)
<agg>
tantalum polymer caps are a bit better about catching fire at least (not that that mouser part is such a thing)
<agg>
about not catching fire, I guess I should say
<agg>
I wish aluminium electrolytics had less annoying packages... why can't they give them big pads
<d1b2>
<DX-MON> yeah.. that's a mood, seeing how the tiny pads makes for higher inductance
<agg>
even really really big smd electrolytics are just scaled up small packages with the same annoying pads
<d1b2>
<konsgn[no-Mic]> speaking of it, in the mini, imma see if i can fit it on the board
<d1b2>
<konsgn[no-Mic]> as a replacement for the electrolytic
<d1b2>
<konsgn[no-Mic]> ... yes i realize tantalum's are a type of electrolytic.... as of 20 min ago when i found that out.
<d1b2>
<konsgn[no-Mic]> ... found that out again*
<d1b2>
<konsgn[no-Mic]> that's the great thing about 7343 capacitor standard sizes.. there's so many to choose from in kicad.
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<d1b2>
<brainstorm> How fast is the SA applet in the Glasgow? Can it capture address line changes from an 45ns SRAM, buffer them and send them to the PC?
<whitequark>
SA?
<whitequark>
if you mean LA, 45 ns pulse size means ~44 MHz sample rate, and the current choice is 48 MHz, so just barely fast enough
<whitequark>
you'll probably bump into throughput but go ahead and try it
<d1b2>
<brainstorm> Ah, sorry, yes, LA. Thanks, I'll do 🙂
<d1b2>
<brainstorm> If there's a more sensible way to setup the capture I'm all eyes 🙂
<whitequark>
that probably works
<whitequark>
synchronizing might be a bit tricky. capture the same pulse with the glasgow sync port and your scope; use --port SAB and then sync becomes channel 0 in the LA applet
<d1b2>
<brainstorm> ... just realised that sniffing the 16 address lines first might help me determine how many wires I need, I doubt the MCU is accessing the entire address space, doh.... not to mention, exacly, sync between LAs can be tricky.
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<electronic_eel>
@konsgn[no-Mic] I recommended using a tvs diode array for each usb-c connector, even if they are in parallel. The reason is that you want to catch esd pulses as early as possible, so that they can't get onto your board where they could inductively couple into other signal lines.
<electronic_eel>
re ceramic vs. polymer electrolytic caps: the cap is intended for bulk capacitance to prevent voltage droop on the 5v rail when a usb device is plugged in.
<electronic_eel>
to get the 150µF at 5v you'd need an array of several ceramic caps. they would take about the same space on the pcb, but would save in height
<electronic_eel>
but height is not critical in this design (as far as i see it)
<electronic_eel>
but ceramics would have the downside as being more expensive and prone to cracking. also they'll have a larger inrush current: at 5v the capacitance will be for example 25% less than initially. so you'd need to parallel more to compensate. but at 0v they will now have more capacitance, resulting in a bigger inrush current when activating the 5v rail
<electronic_eel>
so i think for this usecase polymer electrolytic is a better match
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<electronic_eel>
@rwhitby when looking at your updated design i saw 3 things:
<electronic_eel>
1) silkscreen label size on the jumpers. you use 0.5/0.5/0.125. this will barely be legible and on the fringe of what jlcpcb can do.
<electronic_eel>
on glasgow revC2 we have some text in 0.6/0.6/0.15 (for example the "ESD PROTECTION" label). this is just legible and you can see rastering artefacts beginning to distort the text
<electronic_eel>
i would not go below that and suggest using something bigger. 0.8/0.8/0.15 would be reasonable
<d1b2>
<rwhitby> Ok
<electronic_eel>
2) ground plane. the ground plane is now cut up by the 5v trace on the right side. did you consider going 4 layer? it has really come down in price so i suggest using that. will make your layout easier too
<d1b2>
<rwhitby> Yeah, was thinking about that recently. Since board is nothing in the total cost.
<electronic_eel>
exactly. even if you want to solder it up yourself and just oder the pcbs at jlc it is just like $7 or something like that. shipping is often more expensive than the pcbs
<d1b2>
<rwhitby> For 4 layer I put GND as 2nd and power rails as 3rd?
<electronic_eel>
yes, this would be an easy stackup without much effort.
<electronic_eel>
if you really want to optimize for emi you could do other layer assignments, but i don't think this is worth it here
<d1b2>
<rwhitby> Ok
<electronic_eel>
3) i did not have the spoons to really read through the FUSB302B datasheet and try to understand all the registers and such. that would probably also require learning more about pd
<d1b2>
<rwhitby> I got that bit covered, and am prototyping that on breadboard now.
<electronic_eel>
but i saw that the reference schematics (page 30) recommends capacitors of 200 to 600 pF on CC1 and CC2.
<d1b2>
<rwhitby> Hmm, will look into that.
<electronic_eel>
don't know why exactly they are there, but it could have to do with improving accurracy of the comparators
<d1b2>
<rwhitby> May help BMC decoding too.
<d1b2>
<rwhitby> I'll put them in.
<electronic_eel>
i'd use 200pF then. because when you snoop, the other devices will also have their caps in parallel
<d1b2>
<rwhitby> Yep
<electronic_eel>
and too much capacitance will ruin data transfer
<d1b2>
<rwhitby> Is there anything in the layout which is dodgy? Is my Vbus thick enough now?
<d1b2>
<rwhitby> I guess I can really go to town on Vbus on 4 layers
<electronic_eel>
you have 0.6mm for vbus now. that seems reasonable to me
<electronic_eel>
yes, you can even make it wider on 4l
<d1b2>
<rwhitby> I fixed all the via placements too.
<electronic_eel>
yes, they look good to me now
<electronic_eel>
only thing that i saw is that the ground plane is cut up on several locations. going to 4l will fix that properly
<d1b2>
<rwhitby> Cost comes out to about AUD $100 for 10 boards assembled.
<d1b2>
<rwhitby> It's all the extended part fees that drive it up.
<d1b2>
<rwhitby> The Sot 23s I could probably solder easily myself.
<electronic_eel>
i plan to build one of your addons, but will solder it myself. this is an easy design without any complicated to solder parts or too many parts to make it unreasonable
<electronic_eel>
nice evening project to relax
<d1b2>
<rwhitby> Oh I'm happy to send you a couple for all your help.
<electronic_eel>
you are from australia, aren't you? i'm in germany. shipping costs will probably be expensive
<d1b2>
<rwhitby> Yep
<electronic_eel>
if you still want to send me one, thank you very much!
<d1b2>
<rwhitby> I do.
<electronic_eel>
there was some talk about rounded edges here iirc.
<electronic_eel>
currently you have round edges on all 4 corners
<electronic_eel>
you could just round the lower corners, so that their rounding lines up with the glasgow pcb
<electronic_eel>
and leave the upper corners sharp 90°
<electronic_eel>
to emphasise how to plug it in. but this will only work if the user has their glasgow bare, not in the al case
<electronic_eel>
and since the al case looks really nice and will probably be handy, i guess most people will soon use one
<electronic_eel>
so not really decided yet if it is worth it
<electronic_eel>
the al case has rounded corners too
<d1b2>
<TomKeddie> @rwhitby I'd like to buy one from you. It looks like about $AU24 postage to me (Canada V5K1X9). Once you get the boards back and know the full cost with customs etc let me know the damage. Nice design.
<electronic_eel>
pd creeps into more and more devices, so i think more people want tools to debug it. maybe esden wants to stock these addons in the 1bitsquared store too?
<d1b2>
<rwhitby> @TomKeddie will do
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<d1b2>
<rwhitby> For the internal power plane, I should just split it up into voltage regions, right? Try to make contiguous non-overlapping regions for each different voltage rail?
<d1b2>
<rwhitby> left hand side 3.3V, right hand side 5V, middle VBUS, 1.2v somewhere maybe.
<d1b2>
<rwhitby> Is it better to just do thick traces for power plane like the left hand side and middle, or a filled region like the right hand side?