15:55 <d1b2> <sharebrained> I just scanned through it (I’ve recently made my own applet, so it’s fresh in my mind), and it looks good to me. If you haven’t already, take a look at the LUNA source. I learned a ton of clever things from that codebase, too. Especially how to formulate concise tests and run simulations.

20:13 <akm57[m]> Hello, I'm new here. was sent a link via reddit, never used this platform before. How are we all?

20:33 <d1b2> <DX-MON> @sharebrained thanks for giving it a look 🙂 The sims I have (sim-interactive.py and sim-sniffer.py) are already fairly complete based on real data, however I take your point and will further dive Luna's code base at some point

20:34 <d1b2> <DX-MON> (shame sim-interactive.py takes 12m to complete on a 2700X.. it's a rather chonky sim and pysim has a time dealing with it.. it also outright crashes if used with the experimental cxxsim branch)

20:47 <fest> reinis@mjolnir:~$ glasgow run memory-25x --port A -V 3.3 identify

20:47 <fest> shreg_o = Signal(8)

20:47 <fest> glasgow/applet/interface/spi_controller/__init__.py:88: DriverConflict: Signal '(sig shreg_o)' is driven from multiple fragments: top.multiplexer.<unnamed #0>.<unnamed #3>, top.multiplexer.<unnamed #0>.<unnamed #3>.fsm; hierarchy will be flattened

20:48 <fest> is this warning supposed to be there?

20:48 <whitequark[m]> it's normal

20:48 <whitequark[m]> will be fixed as a part of refactoring later

20:55 <fest> yeah, crappy jumper wires :/

21:00 <whitequark[m]> yep