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17:04
<
gruetzkopf >
hm, are FSM state transitions clocked, and if yes, from what clock source?
17:06
<
vup >
gruetzkopf: in nmigen? you can give the `m.FSM` a `domain="domainname"` argument
17:06
<
gruetzkopf >
thanks!
17:16
<
gruetzkopf >
ah too bad - glasgows uart libraryis still on nmigen.compat
17:17
<
gruetzkopf >
how did i not notice this before
17:18
<
d1b2 >
<Attie> shouldn't be... i think that's one of the ones i updated
17:18
<
d1b2 >
<Attie> are you on main?
17:22
<
gruetzkopf >
i was supposed to be, apparently my IDE overwrote with a stale version
17:22
<
gruetzkopf >
(looking at diffs)
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<
gruetzkopf >
hm, can i easily use the user LEDs yet (i need to look at an internal signal and i'm too fast for --trace, if not i'll just pull it to a normal io)
19:03
<
gruetzkopf >
ah, neat
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19:32
<
fest >
can a clockdomain be created from an external pin?
19:33
<
vup >
fest: for nmigen: `m.domains += ClockDomain("thename")`, then `m.d.comb += ClockSignal("thename").eq(the_external_pin_signal)`
19:35
<
fest >
oh, that seems almost too easy
20:02
<
gruetzkopf >
003c75c0 00 00 00 ce fb 79 03 00 00 19 89 ff 81 7a ff 81 |.....y.......z..|
20:02
<
gruetzkopf >
003c75b0 00 00 00 00 00 00 00 00 00 00 00 4f 67 67 00 00 |...........Ogg..|
20:02
<
gruetzkopf >
003c75d0 44 52 ff ff ba ff 88 ff 9d ff 9e 47 49 59 ff 70 |DR.........GIY.p|
20:03
<
gruetzkopf >
ha, i'm getting close. now to read up on how i
*properly* get the data across the clock domain barrier
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<
gruetzkopf >
(i'm only missing whole bytes, and i'm choosing to view that as a good thing)
20:39
<
gruetzkopf >
(into the AsyncFIFO it goes)
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