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<anarsoul|2>
cwabbott: so I did some experiments and looks like scheduler is OK with series of st_var with ld_uni as predecessor but it's not OK with st_var(ld_reg)
<anarsoul|2>
series of st_var(ld_reg)
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<cwabbott>
anarsoul|2: yeah, that's one of the problem cases
<cwabbott>
what happens is kinda complicated, but I'll try to explain... what happens is that there are a lot of ld_reg waiting to be scheduled, some of which have been spilled
<cwabbott>
now, when we create the st_reg node when spilling, we have to add false dependencies on any ld_reg in the original shader so that their live ranges don't overlap
<cwabbott>
so, what happens is that we successfully schedule a spill st_reg, but the ld_reg child isn't fully ready because it's blocked on another spill node due to the false dependency
<cwabbott>
and, the scheduler currently doesn't have any way to keep track of *which* st_reg needs to be scheduled for progress to be made, so it kinda flails around scheduling other ones until the ld_reg is spilled again
<cwabbott>
now, as to why the ld_reg are spilled at all, it's again because of the fake dependencies... ld_reg can't always be scheduled right away which leads to other kinds of infinite loops unless they can be spilled
<cwabbott>
I haven't seen the trace but that issue is probably what you're running into
<cwabbott>
actually, I don't remember if the change to make ld_reg nodes spillable made it to master, so you might be running into the original "can't spill ld_reg nodes" problem
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<anarsoul|2>
cwabbott: there's no ld_reg spilling in master yet
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<anarsoul|2>
cwabbott: I haven't checked yet, but I think we also need to make regalloc smarter. We can load only 2 vec4 registers per instruction, but if I understand correctly regalloc considers each component as a float reg
<anarsoul|2>
so if float regs aren't grouped properly we end up with only 2 float regs accessible in worst case.
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