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10:19
<
chewitt >
armoon: hello :)
10:19
<
armoon >
i just want to discuss the issue with my patch
10:20
<
chewitt >
ahh, you want real developers then, not me :)
10:20
<
armoon >
I will wait to resolve my query
10:22
<
chewitt >
@jbrunet @narmstrong ^
10:24
<
armoon >
well I also trying to understand the clk structure for Amlogic drivers
10:25
<
narmstrong >
armoon: sorry I don’t understand what’s your query
10:30
<
armoon >
it's my fault, what I am tying to say is as per the S922X datasheet have HHI_SYS_CPU_CLK_CNTL0 0x67 have enable/disable field Dyn_enable bit 26
10:40
<
armoon >
Is their any way to control HHI_SYS_CPUB_CLK_CNTL field
10:41
<
armoon >
I might be wrong in my understating on the clk frame work
10:51
<
armoon >
sorry about this, sorry of the noise,
11:05
<
armoon >
@narmstrong plz try to submit the patch, because I feel embarrassed
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<
narmstrong >
I don’t understand
11:15
<
narmstrong >
This bit is handled by the &meson_clk_cpu_dyndiv ops
11:15
<
narmstrong >
It’s not a gate, it’s used to take in account the dyn_div divider part in account
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