ChanServ changed the topic of #linux-rockchip to: Rockchip development discussion | Wiki at http://linux-rockchip.info | Logs at http://irclog.whitequark.org/linux-rockchip | ML at http://groups.google.com/group/linux-rockchip
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<karlp> heh, the amazone page says it has an intel rock chip 3288, and then the line for "processor brand" it says, "all winner"
<amstan> karlp: fail
<amstan> karlp: wait, where?
<karlp> in "product information"
<karlp> 2gig doesn't say "intel rockchip" but they both say processor brand is all winner
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<naobsd> haha
<amstan> karlp: where did you see "intel rock chip"?
<karlp> product information (the columns" says all winner, "product description" just above it, for the 4 gig only, says intel rockchip
<karlp> Product Description
<karlp> Capacity: 4GB RAM
<karlp> ASUS Chromebook C201PA-DS02 11.6" Laptop (Navy Blue), Intel Rock chip 3288-C Quad- Core 1.8GHz processor, 4GB DDR3 on board, 16GB SSD + TPM, 802.11AC, Bluetooth 4.0, Chrome OS
<amstan> wow
<karlp> I mean, they left out mediatek and amlogic, and poor amd!
<amstan> karlp: well, thanks
<karlp> the 2gig only dos rockchip+allwinner, doesn't say intel before rockchip in the description
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<Tony__> is there 4.2.2 for rk3288 ?
<Tony__> I want to use 4.2.2 replace 4.4.2 for rk3288.
<Tony__> I try to force use 4.2.2 sdk of 3188, it can't works fine.
<Tony__> GPU can not works fine.
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<Tony__> who can give me a hand ?
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<naobsd> Tony__: I guess no one tried it
<Tony__> naobsd, why ?
<Tony__> ;P
<Tony__> naobsd, this is real difficult for me to do that, RK have not release any 4.2.2 for rk3288.
<Tony__> naobsd, about GPU, one is Mali-400, other one is Mali-T764.
<Tony__> naobsd, I tried replace the /system/lib/ files with 4.4's .
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<Tony__> naobsd, I tried to disable GPU, and use gralloc.default.so and hwcomposer.default.so.
<Tony__> Is that possible disable GPU ?
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<c0d3z3r0> mmind00: I reworked the act8846 patch but after some more testing I think that power cycling the act8846 on the radxa rock is not enough. every few reboots there is again a kernel panic. when resetting the board by reset button directly after restart I can reboot multiple times without any kernel panic
<mmind00> c0d3z3r0: so I'd guess still something with the clocks or so
<c0d3z3r0> mmind00: I took a look to the act8846 datasheet. pressing the reset button is the same as resetting it through software… so it should actually work. strange..
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<mmind00> c0d3z3r0: hmm, the act8846 datasheet only mentions the regulators being turned off and on, but not if the settings are reset too [or I'm blind :-) ]
<mmind00> c0d3z3r0: and from the RadxaRock schematics it looks like the reset-button actually toggles the PWRHOLD input of the act8846
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<mmind00> c0d3z3r0: as it seems the undervolting of whatever happens when the other cores are powered on, can you try commenting the enable-method in the dts, try to boot and check the initial regulator output? [normally you should get output like "vcc_something: xxx mV <---> yyy mV at zzz mV" when the act8846 gets probed, so we can see what voltages it has during boot?
<c0d3z3r0> mmind00: yes, I'll try
<c0d3z3r0> mmind00: what enable method do you mean?
<mmind00> c0d3z3r0: arch/arm/boot/dts/rk3188.dtsi -> cpus -> cpu@0 -> enable-method
<mmind00> c0d3z3r0: this simply disables smp :-)
<c0d3z3r0> mmind00: ah yeah didn't find it in rk3188-* :)
<c0d3z3r0> mmind00: commented that out an rebooting works just nicely but there are no vcc messages
<mmind00> c0d3z3r0: ok, so I guess we're really undervolting the cpu ... can you try enabling CONFIG_REGULATOR_DEBUG and then post a "dmesg" somewhere please?
<c0d3z3r0> yep
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<c0d3z3r0> the second last differs
<c0d3z3r0> 1350 mV instead of 1000 mV
<c0d3z3r0> after the kernel panic timeout the restart handler did a act8846 power cycle and the voltage is again 1000 mV
<mmind00> c0d3z3r0: hmm 1.35V would indicate it running at 1.6GHz at the time ... ist this reproducable? [i.e. is the voltage similar on all panics?)
<mmind00> another test: after a sucessful boot, can you try a "cat 1608000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq" and see if it runs stable at 1.6GHz at all?
<c0d3z3r0> oh bad.. most kernel panics happen before the voltage debug :/
<c0d3z3r0> after booting the frequency is already set to 1.61 GHz
<c0d3z3r0> cpufreq governor is ondemand
<c0d3z3r0> again no voltages … https://paste.mniewoehner.de/uER/
<c0d3z3r0> mmind00: another interesting thing… the clock is running way too fast.. 2 seconds per 1 second and it sometimes skips 2 seconds at once o.O
<mmind00> c0d3z3r0: all the time?
<c0d3z3r0> yes
<c0d3z3r0> and it seems to get faster… now it skips 2 seconds all the time
<c0d3z3r0> ah no. that was my fault. i started watch without -n1. it's not getting faster but it's too fast
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<naobsd> with cpufreq, clocksource must not be arm generic timer
<naobsd> ^on rk3188
<naobsd> on rk3066 there is dwc timer, on rk3288 there is arch timer, both are fixed freq, but generic timer is not fixed with cpufreq
<c0d3z3r0> naobsd: where can this be changed?
<naobsd> rockchip-timer should work as clocksource
<naobsd> ^on rk3188
<naobsd> c0d3z3r0: btw, when kernel got panic during reboot? I thought it happened after power-cycle, but VDD_ARM 1.35V is strange
<c0d3z3r0> naobsd: the kernel panic on every reboot happened because there was no power cylce. with the patch the act8846 does a power cycle on restart but it seems that this isn't enough because there are kernel panics after some (2-3) reboots
<naobsd> well
<naobsd> I want to know _where_ panic happen more specifically
<c0d3z3r0> after the reboot / power cycle while booting again
<c0d3z3r0> reboot -> power cycle -> boot -> kernel panic
<naobsd> I see
<naobsd> what happened if you set cpufreq 1.6G manually before reboot?
<c0d3z3r0> cpufreq is always 1.6G. would setting it again change anything?
<naobsd> always? with ondemand governor?
<c0d3z3r0> yes
<naobsd> why?
<naobsd> (I'm talking about cpufreq just before reboot)
<c0d3z3r0> I don't know :D
<c0d3z3r0> 312 MHz:1,71%, 504 MHz:0,09%, 600 MHz:0,22%, 816 MHz:0,22%, 1.01 GHz:0,80%, 1.20 GHz:0,44%, 1.42 GHz:0,27%, 1.61 GHz:96,25% (49)
<c0d3z3r0> driver is cpufreq-dt
<naobsd> it seems "not always"...
<c0d3z3r0> yeah didn't check the statistics before
<naobsd> I want to know what happen if "cat 1608000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq" then reboot
<naobsd> (I assume both min/max are 1.6G in this case)
<naobsd> and what happen if both min/max are lowest too
<c0d3z3r0> booting just fine in the first case
<naobsd> is VDD_ARM 1V?
<c0d3z3r0> VDD_ARM: 875 <--> 1350 mV at 1350 mV
<naobsd> sounds like power cycle doesn't reset output voltage
<c0d3z3r0> when setting cpufreq to 312 mhz and rebooting we have 1,0V and no panic
<naobsd> oh wait, what we thought was, lower freq/lower voltage causes panic after reboot
<naobsd> we misunderstood something
<c0d3z3r0> we had a panic at 1350 mV a while ago
<c0d3z3r0> 1000mV there was no panic at all
<c0d3z3r0> maybe we get a panic when frequency is 312 and voltage is 1,35V?
<naobsd> ah I remembered one thing
<naobsd> you should wait 8ms or so after SIPC assert
<naobsd> cheking datasheet...
<c0d3z3r0> for debugging and testing I added msleep(1000); after the i2c command
<c0d3z3r0> that doesn't change anything
<naobsd> maybe mdelay()
<naobsd> but probably you're right, power cycle doesn't reset voltage...
<naobsd> I should try some myself, but I couldn't get time for a while... I couldn't touch my rockchip boards in several days :(
<c0d3z3r0> the default values at boot time come from the dts, rigth?
<naobsd> I think only mix/max value are described
<c0d3z3r0> mhh wait
<c0d3z3r0> doesn't the bootloader set the voltages at boot time?
<naobsd> probably not
<c0d3z3r0> maybe we should set VDD_ARM to 1V before power cycle
<naobsd> possibly
<naobsd> I still not sure what happen with SIPC
<naobsd> but what I want is "reset all output to initial state"
<naobsd> want -> expected
<naobsd> there is watchdog reset, it might do something, but it needs some secs (not msec) to work
<c0d3z3r0> "When watchdog timer expires, the PMU commence a power cycle."
<c0d3z3r0> I excpect this to be the same as sipc
<naobsd> well, I have to go out soon
<c0d3z3r0> the reset buttons see
<c0d3z3r0> *seems to only cut the power output
<c0d3z3r0> so there isn't any reset to default values as well
<naobsd> hmm.... I misunderstood some more things :(
<naobsd> sorry, bye
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