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<ramcq>
is "vpu-service" in the rockchip kernel the custom rockchip interface?
<ramcq>
and rockchip-rga is the v4l2 m2m driver for decode that CrOS uses?
<ramcq>
or there is a different driver that does v4l m2m slice?
<phh>
ramcq: rga isn't for decode, it's for things like scaling/color conversion/... afaik it shouldn't be used as part of video decoding pipeline, because the VPU+LCDC is already enough
<phh>
though cros indeed has a v4l2 m2m decode driver (it supports only h264 and vp8 though)
<ramcq>
well that explains why this v4l code isn't working :D
* ramcq
has a patched chromium to turn back on the cros code
<ramcq>
need to dig the kernel config a bit more than
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<Ke>
I have now a spi nor, how could I connect it to firefly-rk3399 to make it bootable
<Ke>
just the normal gpio spi connections?
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<Ke>
if I put "something" to the chip I have and connect it to spi1 as documented in firefly gpio interfaces, I get no output on serial, not even the hw greetings
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<Ke>
wonder if the spi is read before any initialization is done
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<mmind00>
Ke: I think you'll only ever get output once the spl has configured the uart ... maskrom itself doesn't talk
<Ke>
mmind00: are you positive, I get output, if I disconnect sd and spi and disable the emmc
<Ke>
the only configuration I do not get output is, when spi-nor is connected to spi1
<mmind00>
Ke: not 100%, but I never got anything from maskrom on all chips I had so far
<Ke>
I wouldn't have thought so, but where do you think the code is loaded from?
<mmind00>
Ke: don't know ... also I don't know what sort of output you get ;-)
<Ke>
I can pastebin
<mmind00>
ok :-) .... because the maskrom area is often very small, so I don't think they'd keep uart init + text in there
<mmind00>
but it is of course possible that it changed with say the rk3399
<Ke>
could it be that the eMMC is accessible with spi mode, but the switch to eMMC native mode fails?
<mmind00>
Ke: that definitly looks like the regular Rockchip 1st stage loader ... I really don't think that DDR-init and friends will be sitting in the maskrom
<mmind00>
especially as it also talks about the ATF there (TrustBL ...)
<aalm>
mmind00, what do you think about the @rockchip push to break ie. rk3188 in u-boot w/untested code? :D
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<mmind00>
aalm: I don't follow uboot development that closely so you will have to enlighten me ... but also please don't call it a "push to break..." ... breakage in 99% of cases is unintentional
<aalm>
patches to remove the rk_timer to be replaced w/"arm arch timer", which doesn't exist on Cortex-A9, they should have known, right?
<maz>
aalm: could really be a honest mistake done by an engineer that has been task to improve support for recent SoCs, and didn't know about TWD...
<aalm>
i hope so
<maz>
aalm: and frankly, I'd rather forget A9 altogether.
<mmind00>
aalm: what maz says ... i.e. the rk3188 is from 2013 or earlier ... I don't even know if the developer was with Rockchip back then
<mmind00>
aalm: and when I did the initial rk3188 support, Kever did a lot of work in tracking down the maskrom oddities it has ... including finding the maskrom-developer who knew
<Ke>
mmind00: thanks anyway, any idea, is there some instructions on building spi bootable rom?
<mmind00>
Ke: sadly no idea
<Ke>
ok, thanks
<Ke>
I could perhaps just yank that broken eMMC off, perhaps it could help me do SD boot
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<beeble_>
Ke: you did a mkimage with the rkspi paramater?
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<beeble_>
and as mmind00 said, thats miniloader you see
<beeble_>
and at what offset are you flashing u-boot into the spi nor?
<vagrantc>
beeble_: i don't use that interface often
<vagrantc>
beeble_: but i do recall vague mention of it
<beeble_>
whee, buster has a new picocom
<beeble_>
finally higher baudrates
<vagrantc>
screen a while ago too
<vagrantc>
beeble_: the armhf files link appears to work fine ... so i'm guessing some cache is just outdated, since the arm64 package wasn't always available
* vagrantc
is tempted to try xypron's script and see if it works
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