05:29 <hanetzer> s_frit: you're prolly gonna have a bad time with that

05:41 <s_frit> hanetzer: hence why i am asking first. what's your theory?

05:42 <hanetzer> s_frit: my theory is ARM SoC are really close to being an entire mobo in a package, and one snafu will put you out of the whole thing.

05:43 <s_frit> hanetzer: do you know if the SoC is likely to have more than one silicon die?

05:43 <s_frit> i was thinking of trying to find a dead one to experiment on

05:43 <hanetzer> s_frit: this one? don't think so, but some SoC have dram in the package as well :P

21:05 <mmind00> asciilifeform: the comment section on your blog fails due to the captcha-service being shutdown

21:05 <mmind00> asciilifeform: anyway, what I wanted to write: "Just to fix the misunderstanding regarding the log output: The Cr50 most likely did nothing to the generated output. There can not be any "Rockchip DDR init info" as the device uses coreboot exclusivly and the mass-production units start with the coreboot console output disabled. To get bootloader output you would need to build and flash a dev-mode coreboot to the device."

21:28 <asciilifeform> mmind00: the first 4080 bytes of the rom is ddr init.

21:29 <asciilifeform> iirc the vendor docs call it 'bootloader'

21:29 <asciilifeform> there is also the rk33 thing ( arm 'trustzone' crapola ) after it

21:30 <asciilifeform> and yes i know that the vendor's rom does not produce uart output on apuart. was speaking of stock uboot, which (if it actually ran, which it thus far does not) ~does~.

21:31 <asciilifeform> https://github.com/rockchip-linux/rkbin/tree/29mirror/bin/rk33 << the rk manufacturer's init bins

21:31 <asciilifeform> (none of them correspond to the one in c101pa factory rom)

21:31 <asciilifeform> http://www.loper-os.org/pub/current_c101pa_main.bin << my unit's factory rom, 8MB

21:34 <asciilifeform> last night i set out to try & replicate google's build of the boot rom, but so far no luck, the docs are nonexistent and it seems to want a nonstandard toolchain (vs ordinary aarch64 gcc) and various env paths to ???

21:34 <asciilifeform> all i found so far was https://www.chromium.org/chromium-os/2014-firmware-summit , which is worse than useless

21:38 <asciilifeform> my objective for this box is to lift whatever driver magic required from google's rom, and get ordinary uboot, which loads ordinary (non-signed) kernels from a non-googlistic partition, like exists on every other rockchip board.

22:08 <mmind00> asciilifeform: that's all part of the vendor-uboot solution ... if you look at mainline uboot you will find source-ful DDR init code inside uboot itself ... coreboot also does its own ddr init

22:09 <mmind00> asciilifeform: aka both mainline uboot-spl and coreboot are the first stage loaders which the rom of the soc loads

22:12 <mmind00> asciilifeform: as for building a coreboot boot image, you'll need a ChromeOS repo https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md#Get-the-Source first

22:13 <mmind00> asciilifeform: ideally using the firmware branch ... which is "firmware-gru-8785.B"

22:14 <mmind00> asciilifeform: then the chromeos chroot, which is their standard way of building things https://chromium.googlesource.com/chromiumos/docs/+/master/developer_guide.md#Building-Chromium-OS

22:15 <mmind00> asciilifeform: and if I remember correctly, I did a "emerge bootimage" or something like that to build ... which will create mp, dev and netboot images

23:55 <asciilifeform> ty mmind00 , i will try this recipe