09:57 <inode> mmind00: if you still have access to an rk322x TRM, please could you confirm some gpu clock selection/gating assumptions that i've deduced from looking at develop-4.4's clk-rk3228.h, mainline's clk-rk3328.h and the rk3328 TRM?

09:58 <mmind00> inode: sure

09:58 <inode> 1. (a) bits 5-6 of CRU_CLKSEL_CON34: PLL source selected for aclk_gpu? (b) value 2 selects HDMI PHY?

09:58 <inode> 2. bit 13 of CRU_CLKGATE_CON3: gate of aclk_gpu's PLL source?

09:58 <inode> 3. bit 14 of CRU_CLKGATE_CON7: gate of aclk_gpu clock?

09:58 <inode> 3. bit 15 of CRU_CLKGATE_CON7: gate of aclk_gpu_niu clock?

09:59 <inode> ^ s/3/4/ :/

09:59 <mmind00> 1. correct

10:00 <mmind00> (for reference selectors are 0 cpll, 1 gpll, 2 hdmiphy, 3 usbphy-480m)

10:01 <mmind00> 2. aclk_gpu_src_gate ... so looks like yes

10:01 <mmind00> 3+4 also correct

10:01 <inode> thanks

10:03 <inode> these assumptions have finally allowed lima to work after patching clk-rk3228.h - no more rcu_sched stalls and sudden halting

10:04 <mmind00> inode: oh cool ... which change was necessary?

10:18 <inode> it seems that the "aclk_gpu" and "aclk_gpu_noc" gates were referencing gate offset RK2928_CLKGATE_CON(13) instead of RK2928_CLKGATE_CON(7)

10:18 <inode> but that wasn't enough, i then changed the declaration of "aclk_gpu_pre" from COMPOSITE_NOGATE parented by "mux_aclk_gpu_pre_p", to COMPOSITE with the "mux_pll_src_4plls_p" parent and gate offset RK2928_CLKGATE_CON(13) and shift 13

10:19 <inode> this matches what develop-4.4 does

10:29 <inode> so in this state there are gate declarations (cpll_gpu, gpll_gpu, hdmiphy_gpu, usb480m_gpu) associated with bit 13 of CRU_CLKGATE_CON3 that are now unused - should i leave them entact or remove them when submitting a patch?

10:43 <mmind00> inode: had to look up the clock diagram for this ... in the schematic drawing it indeed looks pretty strange, with separate gates for the 4 aclk_src inputs, but all being gate3:13

10:45 <mmind00> inode: and these gates don't seem to actually exist, so should be removed ... especially when they even reference the same gate bit, as this might cause even more issues down the road

10:47 <mmind00> inode: "and gate offset RK2928_CLKGATE_CON(13) and shift 13" is a part I don't understand though ... I guess you meant gate_con3:13 .... gatecon13:13 would be the hclk_vop_noc_gate (for the vops bus interface)

10:50 <inode> yes sorry, gate_con3:13 :)