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<KotCzarny>
tuxd3v: you should try dell e7240, it's a very nice machine, and can be had for ~120-150usd
<KotCzarny>
windoze is telling me about 13h on battery, but i havent got time to test it yet
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<tuxd3v>
KotCzarny, that is a amd64 I believe, I wanted a arm64 :)
<KotCzarny>
it's ulv cpu
<KotCzarny>
really amazing what it can do in its tdp envelope
<KotCzarny>
and it's ultrabook, meaning you get 12" beauty that still has real cpu power inside
<KotCzarny>
the only gotcha is that it can support 16gb max
<KotCzarny>
i wonder why no one made fruit pi board with ram slot instead of soldered
<KotCzarny>
low capacity ram cards are dirt cheap
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<JohnDoe_71Rus>
KotCzarny: open kikstarter project )
<anarsoul>
KotCzarny: because it's difficult
<anarsoul>
also you'll need to invest some money into ram init in bootloader since it doesn't read out SPD to configure RAM
<KotCzarny>
anarsoul, but isnt ram autoconfigured on soldered-on solution anyway?
<KotCzarny>
unelss sodimms add some layer between chips and controller
<anarsoul>
nope, frequency and timings are hardcoded
<KotCzarny>
so it would be as easy as changing few items in uboot config?
<anarsoul>
well, yes if you get hardware right
<anarsoul>
but it's difficult
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<mripard>
jernej: which AXP driver is loaded through platform_device_id?
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<wens>
mripard: regulators for example
<wens>
jernej: if the sub-device needs a device node (for instance it exports something through the device tree), then you would have a device node and use compatible for probing
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<willmore>
KotCzarny, ever look at a PC motherboard memory compatability list? It's a complex problem even in that space. Trying to do that on a budget? Yikes, good luck! There's just so much variability with the different memory chips that DRAM init would be huge and flakey.
<KotCzarny>
so all those ranks/timings require smarter memory controller?
<willmore>
They generally require a very flexable one and a bunch of code to adapt it to the memory in question.
<willmore>
Most SoCs don't have that flexable of a memory controller.
<plaes>
doesn't dimms have some kind of storage that include the timing information for bios?
<KotCzarny>
so it's not something that allwinner + some code in uboot would fix?
<willmore>
And the init code is always a 'just do this' kind of blob.
<willmore>
plaes, yes, they do, but it's not a detailed and accurate as you'd like--there's timing delays on the board that don't fit into it exactly.
<willmore>
KotCzarny, no, it's way more complex than that.
<KotCzarny>
or asking in another way, dram controller in allwinner socs isnt that flexible?
<willmore>
I don't believe it is.
<willmore>
It didn't need to be as there aren't common applications for these types of SoCs where it would need to be.
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<willmore>
It's a waste to design a super flexable DRAM controller when 99% of the time it's not needed.
<willmore>
Costly, power consuming, software compleity kind of waste.
<willmore>
Embedded designs like to use known parts--and can compensate for issues with parts by altering the board layout to tune the timing.
<willmore>
PCs do it the other way around--what do we have and adapt to that.
<willmore>
While SoC says "where's what we and the chip can do, make the PCB adapt the two".
<KotCzarny>
modularity is one of the keys to the success of x86 as it is
<willmore>
Yes it is, but that's because of 40 years of need that the SoC market hasn't had.
<KotCzarny>
and since we already know about electrowaste problem, it would be smart to start reusing some parts
<willmore>
Most SoC layouts--SoC to DRAM--are coppied right out of the reference design. Look at the OpiPC2 where they had to rotate the whole SoC/DRAM complex by a few degrees to get some more space for other stuff. The SoC/DRAM layout was so critical that they didn't risk relaying it out, so they rotated the whole chunk to avoid doing that.
<KotCzarny>
:)
<willmore>
KotCzarny, true, but that has to balance the waste that adding a memory connector and a more complex memory controller (and the board from the SODIMM) will bring.
<KotCzarny>
i bet everyone has a drawer with a bunch of 512M-2G sodimms
<willmore>
Plus, good luck getting the $9 SBC maker to add in the $1 connector when that's about as much as the DRAM already costs.
<willmore>
Yeah, but they're DDR2 and wouldn't work with current DDR3/4 SoCs...
<KotCzarny>
ddr3 are dirt cheap too
<willmore>
cheaper not on a SODIMM. :)
<KotCzarny>
and i think i have all kinds of memories, back to sdr and plain drams
<KotCzarny>
even some socketed graphic drams chips
<montjoie>
this PRNG made me mad, now the first 20bytes are always the same...then random
<montjoie>
note that a PRNG which works randomly is ...
<KotCzarny>
:)
<KotCzarny>
hack the entropy!
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<willmore>
montjoie, no chance the output has a 20 byte header or that a pointer is misaligned? (searching for a possiblity)
<montjoie>
willmore: some days ago it "worked" normaly, but I dont find any change on my side
<montjoie>
but I have another change, the CTR entry got 4bytes random before, now only zeros
<montjoie>
at least the TRNG on H6 seems random for the moment
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<KotCzarny>
you should keep backups
<KotCzarny>
just for comparisons
<willmore>
Yeah, chips changing their behavior from day to day is very disturbing.
<montjoie>
if the TRNG really work, PRNG is useless
<montjoie>
anyway, time to rngtest on lot of output
<willmore>
montjoie, this is still on a bizarre chip, right?
<willmore>
a83t or something esoteric, right?
* willmore
only has A64/H2+/H3/H5/H6
<KotCzarny>
no a10/a20 ?
<willmore>
I wasn't interested in AllWinner that far back.
<KotCzarny>
a20 is pretty nice soc
<willmore>
I may have a little android laptop thing that is an older AllWinner chip, but I don't know where it got to.
<KotCzarny>
expensive as hell too
<willmore>
If I can ever find it, I'll look into getting plain old linux on it. It's got ethernet, so it would be really cute to have it able to do stuff. Pretty sure it has wifi, too.
<willmore>
KotCzarny, why is A20 expensive?
<KotCzarny>
who knows
<KotCzarny>
it's just is
<willmore>
Okay.
<montjoie>
willmore: the prng work on a83t (but trng burp 0 randomly)
<montjoie>
my test are currently on h3 and h6
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<montjoie>
but H6 has different algo numbers for prng/trng, so perhaps a different than other sun8i-ce (vs h3 h5 r40 a64)
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<montjoie>
a10/a20 have prng support since a long time (sun4i-ss)
<montjoie>
I need to finish update on the crypto matrix
<montjoie>
I will push my code tomorow on github if people want to test
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<tuxd3v>
does any one was able to get DVFS on H6?
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