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<apritzel>
prefixcactus: do you have the same DRAM chips on the underside of the SoM as on the upper side?
<apritzel>
prefixcactus: it's 2 on the top, 2 on the bottom, right? The pictures on the website only ever should the top side ...
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<prefixcactus>
yes, there's 4 in total.
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<prefixcactus>
meanwhile, my printf'ing leads me to the conclusion it looks like the #if CONFIG_IS_ENABLED(DM_MMC) blocks don't get compiled in for some reason, even though CONFIG_DM_MMC=y is in .config
<apritzel>
that only applies for U-Boot proper
<apritzel>
the SPL is not using DM_MMC
<apritzel>
the same file gets compiled without the device model framework for the SPL
<prefixcactus>
there are such blocks in spl.c however
<apritzel>
some platforms use DM on the SPL as well
<apritzel>
but we can't afford it, since we have 32KB (mostly) only for the SPL
<apritzel>
it's a bit of a mess, but there is no really good solution, and I rather keep DM out of the sunxi SPL
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<apritzel>
prefixcactus: the register dump you sent yesterday seems to set the rank1 CR register differently to rank0, which *could* mean there are different chips connected to the second rank
<apritzel>
prefixcactus: alternatively there is is a misunderstanding how this register works, and it's either interpreted differently or not in effect at all for some reason
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<pCactus>
apritzel: The chips themselves are definitely all the same
<apritzel>
pCactus: alright, thanks for the confirmation (I was suspecting that, but wanted to make sure)
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<apritzel>
pCactus: and do you have the 1GB or the 2GB version of the module?
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<prefixcactus>
apritzel: 1GB
<apritzel>
right, thanks
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<karlp>
could it be tuning parames for second rank to account for different lengths or anything to the second bank on the other side?
<apritzel>
no, that's the basics of the DRAM matrix layout, like number of row bits
<gediz0x539>
apritzel: just asking out of curiosity, why it is not a good idea keep DM out of sunxi SPL?
<apritzel>
karlp: there are delay values, but per bit, so one would place both chips for the higher word on one side, and the ones for the lower word on the other, then tune the respective bit values
<apritzel>
gediz0x539: I said: "I'd rather keep DM out of the SPL", do you mean that or did we misunderstand each other?
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<karlp>
apritzel:nvm then
<apritzel>
karlp: no worries, thanks for participating!
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