<jernej>
I also extended edid function to check for detailed timings in extension block
<jernej>
now I get video output on my 4k screen on H3
<apritzel>
jernej: oh, nice!
<jernej>
aprizel: that edid improvement would probably help you in A10 driver
<apritzel>
4K at H3: at which resolution? 4K@30p? Or some lower fallback resolution?
<KotCzarny>
wasnt 4k working in libreelec-h3 for quite long time? (thanks to you mostly :)
<KotCzarny>
unless you mean uboot only
<apritzel>
jernej: yeah, I will see what I can pick from there
<jernej>
apritzel: actually, first valid timing is 1080p@60
<apritzel>
KotCzarny: that's about U-Boo
<jernej>
second one is 4k@30, but it's not reached
<apritzel>
jernej: ah, right, you say there are more resolutions in the extension block
<apritzel>
jernej: so we see 4K@60 first, but discard that, because the pixel clock is beyond 297MHz, then look further and find 1080p@60 next, and use that?
<jernej>
yes
<apritzel>
nice!
<apritzel>
I asked uis, but he only reported the 4K@60 resolution in EDID (which I found odd), but I didn't check the extension block, I think
<apritzel>
jernej: I will see how I can replicate this into the A10 driver, thanks!
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<jernej>
use edid_get_timing_validate() function instead of hand rolled from the driver
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<jernej>
code is very similar, no need for duplication
<apritzel>
jernej: do you what it would take to add H6 support to the sunxi-de2 driver? I know you don't *really* care about video in U-Boot, but still ;-)
<apritzel>
do you know* what it would take
<libv>
heh, uboot grew modevalidation then
<jernej>
apritzel: why I wouldn't care? I wrote DE2 support in U-Boot :)
<jernej>
but it's true I have no use for it currently
<jernej>
you need to add TCON TOP handling - only few registers
<jernej>
dw-hdmi uses different PHY, so you would need to add PHY tables from Linux and change init a bit
<jernej>
DE2 and DE3 mixers are extremely similar, mostly you would need just adjust offsets and update code for disabling unused units
<jernej>
this probably means that driver would need switch to DT compatibles to differentiate between DE2/DE3 and different HDMI PHYs
<apritzel>
jernej: I see, thanks
<MoeIcenowy>
apritzel: BTW I'm thinking about sending my asymmetric dual-rank DRAM patch again, w/o RFC
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<apritzel>
MoeIcenowy: oh good, I was about to send it again to the list, to get some final comments
<apritzel>
my plan was to have a closer look at it today, but it seems to be used already by people, so is probably good to go
<jernej>
apritzel: is there any plan to use DM clocks and resets? current approach is pretty messy
<MoeIcenowy>
apritzel: my plan is to include it with the patch to enable dual rank on R40
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<MoeIcenowy>
apritzel: who had Forlinx board?
<MoeIcenowy>
apritzel: I'm sorry to say that just enabling dual_rank regresses on M2 Ultra
<MoeIcenowy>
current code do not detect DRAM rank/width correctly on R40...
<MoeIcenowy>
because R40 cannot do PIR_QSGATE
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<apritzel>
MoeIcenowy: dual rank enablement on M2 Ultra> I was wondering about that, good to have confirmation
<MoeIcenowy>
apritzel: I wrote a dual rank detection routine that works on M2 Ultra
<MoeIcenowy>
but I need to verify it on real dual rank R40
<apritzel>
MoeIcenowy: oh nice! You should have the email address of the guy with the Forlinx board, I Cc:ed him in the email I sent you
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<apritzel>
(he does not seem to be in here atm)
<apritzel>
jernej: yes, I started to look at DT clocks, for DE2 it does not seem to be too complicated
<jernej>
apritzel: do you plan to do it gradually or in one sweep?
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<apritzel>
jernej: DE2 is H3/H5/A64 only anyway atm, right? And it would be only in sunxi_de2_composer_init(), so that could be in one go
<MoeIcenowy>
(currently only reverting a change to enable dual rank on R40)
<MoeIcenowy>
the R40 rank detection code is the 2nd commit, because it relies on a function introduced in asymmetric rank commit, which calculates the size of rank 0 (for getting the base address of rank 1)
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<apritzel>
smaeul: Many thanks for the CPUIDLE wiki page! I wish all of the documentation would be of that quality ...
<smaeul>
right now I'm trying to figure out if I can do core idle in TF-A only, without the latency of SCPI
<smaeul>
cluster idle requires ARISC support, and the SCPI spec requires the implementation to do its own coordination, so I don't think I can
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<KotCzarny>
break the spec then?
<KotCzarny>
i mean 'extend' ;)
<smaeul>
doing state coordination in crust is nice for H3, because then I don't have to also implement it in U-Boot :)
<wens>
looks like libfdt does not fix up aliases when applying overlays
<wens>
(aliases contain the full path of the node referenced instead of a phandle)
<smaeul>
apritzel: you're welcome! that page contains everything I know so far
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