lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
rjo, do BRAMs make sense for shallow and wide memories?
<sb0>
afaik one BRAM element is maximum 32-bit wide but very deep
<sb0>
a shallow and wide memory implemented on BRAM would use a lot of BRAM elements of which only a fraction would be accessible
<rjo>
sb0: 256x32 (depth x width). yes.
<rjo>
sb0: but if you have BRAM to spare, why not use it?
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<rjo>
sb0: i had also stumbled upon that web page. interestingly enough, his last implementatation (FWFT with improved timing) is as large as mine but two cycles larger latency. i would expect timing to be a bit better with his though.
<rjo>
sb0: i posted the two additional FIFOs
<rjo>
sb0: afaict if you have BRAM to spare, and your fifo depth is larger than a very small value (~2) SynchFIFO uses more logic than SyncFIFORelaxed. but yeah. The usecases for SyncFIFORelaxed are uncommon.
<sb0>
rjo, so we just use your latest patches for now?
<sb0>
if any use for SyncFIFORelaxed comes up, it's still in the ML archives...
<sb0>
by the way, the SyncFIFOs I use (in the SDRAM controller) are 8 entries deep
<sb0>
it generally does not make sense to use BRAM for them
<sb0>
(RAM-on-LUTs isn't _that_ bad, since the LUTs themselves are used for read-write storage - it's much more efficient than 1 bit per user flip-flop)
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<larsc>
what's the technical term for always @(posedge clk) if (reset) a <= 1'b0 else begin a <= ...; _b_ <= ...; end
<larsc>
this will implicity make the reset value b be b, which means it's non const