13:41 <ysionneau> mumptai: why not simulating the ip-core instead of making communication between qemu and a HDL simulator

13:42 <ysionneau> I mean, why not writting the IP-core simulation in C inside Qemu, just like it's done for the framebuffer, ethernet core, ac97, uart, flash, ram

13:42 <ysionneau> timers

13:42 <ysionneau> do a qemu model for it

13:42 <mumptai> because that require an additional executable description of the core?

13:43 <mumptai> dunno maybe verilator or similar could be used to generate that model

13:43 <ysionneau> not sure

13:43 <ysionneau> but yes indeed it's a bit of work, depending on what the IP core is doing

13:44 <ysionneau> what's the IP core ?

13:44 <mumptai> yes, but for some the work is okay

13:44 <mumptai> i have some robotics interface stuff

13:46 <ysionneau> in any way, if you can make qemu communicate with an external program, using a unix socket for instance

13:47 <ysionneau> if your hdl simulator can talk via sockets it could be a way to make both of them interact

13:48 <mumptai> that is what i was think in that moment

13:49 <mumptai> but i'm probably never goin to do that, because the resulting solution is likely to be very specilized and timing is likely to be terrible

13:50 <mumptai> and the simulated peripheral is just one step, the stuff connected to that is also kinda important to the system ;-)

14:06 <ysionneau> yeah I se

14:06 <ysionneau> see

14:07 <ysionneau> if timing is important then I guess all of this won't be a proper solution

14:07 <ysionneau> maybe you'd better interface qemu with a FPGA :)

14:07 <ysionneau> via serial port for instance

14:18 <mumptai> rather ethernet or spacewire, but a lot of work down that road is waiting