sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> cr1901_modern, may not be the problem, but you also need to drive the reset signal
<sb0> and reset_less doesn't work because the verilog cpu cores expect a reset signal
<cr1901_modern> sb0: Adding the following line self.comb += [self.cd_sys.rst.eq(0)] did not fix the problem, but that was a good suggestion
<sb0> this line made zero change to the behavior of your code compared to your previous design
<sb0> you need an actual reset pulse
<cr1901_modern> Let me guess... the CPU cores are actually edge triggered resets, aren't they?
<sb0> it's a standard synchronous reset
<sb0> same as in your generated verilog
<cr1901_modern> sb0: Updated to include a pulse signal https://gist.github.com/cr1901/e9ed9ba9e7cf8c791a0d0545125a36e4
<cr1901_modern> Still optimizing away everything lol
<cr1901_modern> sb0: Fixed it... I copied what misoc does by default, but... >>
<cr1901_modern> am unsure why my most recent revision fixed it: https://gist.github.com/cr1901/e9ed9ba9e7cf8c791a0d0545125a36e4/revisions
<GitHub113> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/vrYlz
<GitHub113> migen/master 7b7e70b William D. Jones: migen/build: Add Lattice iCEstick dev board.
<bb-m-labs> build #73 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/73
<bb-m-labs> build #105 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/105
<bb-m-labs> build #420 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/420
<bb-m-labs> build #176 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/176
<bb-m-labs> build #686 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/686
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<GitHub145> artiq/master 5b5c9b2 Robert Jordens: browser: pass mods to applets (closes #434)
<GitHub145> [artiq] jordens pushed 1 new commit to master: https://git.io/vrOm4
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<bb-m-labs> build #421 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/421
<bb-m-labs> build #177 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/177
<GitHub105> [artiq] jordens pushed 2 new commits to master: https://git.io/vrOOF
<GitHub105> artiq/master 633c363 Robert Jordens: browser: rm status bar
<GitHub105> artiq/master fe69712 Robert Jordens: browser: dis/enable analyze/terminate buttons
<bb-m-labs> build #687 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/687
<bb-m-labs> build #422 of artiq-kc705-nist_clock is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-kc705-nist_clock/builds/422
<bb-m-labs> build #178 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/178
<bb-m-labs> build #688 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/688
<rjo> sb0, whitequark: do we need codenames for the artiq releases? the quarks etc?
<whitequark> meh, I wouldn't bother
<sb0> yeah, we have enough fancy names with the hardware project
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