<rjo>
iirc that was sb0. readline is used for the cli tool.
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<mumptai>
is there something like a description of how to develop systems in migen? or is it all still in the flow? any documented best practices?
<rjo>
develop systems? you mean a SoC?
<mumptai>
not necessarily with a cpu and embedded sw, but analogus to what is usually done with HDLs for FPGAs
<rjo>
you write your module(s), you write testbenches for them, simulate them (rinse, repeat) and then you compile it, load it and try it (rinse, repeat). that is the same process as with other HDLs. it's just that the language is different. or what part of the work flow do you mean?
<mumptai>
i'm currently digging my way through the code of migen & misoc, which is okay to do. but, i guess there a things not so obvious, which would be good to know
<rjo>
true. good documentation is a hard thing to come by these days. pretty sure you have found all the important places. the other side to learn from are the designs that make use of migen/misoc.
<mumptai>
i'm used to the typical hdl style with testbenches, and local bottom-up, global top-down approach
<mumptai>
but i guess that tesbenches might actually get easier to do in more elaborate style, than compared to vhdl
<rjo>
for testbenches in migen (to me as somebody how never did much verilog/vhdl) testbenches are really smooth and powerful in migen.
<rjo>
however, a feature i see myself wanting often is to be able to look back in time when doing a simulation. that is, directly access and use a Signal()s history of values. the other HDLs don't have this either but it would not be that hard to offer in migen.
<rjo>
like: "was ACK high at any time since the last STB" without having to write the code that tracks all this manually.
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<mumptai>
i vaguely remember there should be a way in vhdl to delay a signal by a fixed amount of time