sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
rjo, why did you add "self.platform.add_period_constraint(self.rtio.cd_rsys.clk, 8.)"?
<sb0>
self.rtio.cd_rsys.clk is just the system clock, it should already have a 8ns constraint from misoc. is that not the case?
<sb0>
it's an implicit constraint through the PLL, maybe that failed?
<sb0>
(the 125MHz clock is generated from clk200, migen adds a 5ns constraing on clk200, and vivado/ise are supposed to make that 8ns after it goes through the PLL)
<sb0>
*constraint
<sb0>
as for yqis, it looks like a pretty general conference. didn't you say you wanted to talk to phd students/postdocs?
<sb0>
it's also reasonably priced for once, unlike the usual 3- or 4-digit fees of "prestigious" academic conferences
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<ssk1328>
Hi everyone I am GSoC student with TimVideos, I had question about defining multiple sinks for a pipelined actor?
<ssk1328>
This is how I am defining multiple sinks for a FloatAddRGB unit, and further down how I am using it http://paste.ubuntu.com/21109705/
<mithro>
ssk1328: Just ask the question and people will reply if they can. Try and be as detailed as possible and link to code that people can read
<mithro>
ssk1328: Linking to full code on github is better then snippets like that
<ssk1328>
I sense that I am not defining the two sinks correctly, and there is a correct way to do it
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<rjo>
sb0: where is that line?
<rjo>
sb0: iirc i went to yqis a couple years ago. the reason you don't get your knee jerk "too expensive" reaction is that it is more of an invitation basis.
<rjo>
and when i went, i would not have wanted companies to be there. and there are generally none.
<_florent_>
ssk1328: you probably need to connect your signals manually for this case (at least part of), connecting a source to two sink is not correct.
<rjo>
sb0: i remember it being a workshop, less of a conference. and that is directly reflected in the phrasing of their "mission statement"
<rjo>
maybe the layout changed.
<rjo>
i wouldn't want to compare us with d-wave.
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<rjo>
oh. i was at another conference, not that one. but my concern still stands: that conference is for young researchers by young reserchers.
<sb0>
they have Chris Monroe and Sandu Popescu speaking there
<sb0>
so, not completely. and as i said, didn't you mention you wanted to advertise to phd students and postdocs?
<rjo>
the format is described in last year's program. the invited speakers seem to be doing tutorials.
<rjo>
and those are the invited speakers.
<rjo>
the ones filling out the registrations and submitting abstracts are young postdocs and phd students.
<rjo>
yes. but imho the forum to speak to those is dpg or damop. or maybe a more specialized workshop that is not that much targetted at getting young researchers into their fields.
<rjo>
and the cost of the conference registration always seems small compared to the flights and the accommodation, wether it's 60 eur or 200 eur.
<rjo>
anyway. i can give it a shot. barcelona is always nice.
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<GitHub191>
[artiq] sbourdeauducq pushed 4 new commits to master: https://git.io/vKFId
<GitHub191>
artiq/master a89f96e Sebastien Bourdeauducq: runtime: support boards without LEDS
<GitHub191>
artiq/master 7928ee4 Sebastien Bourdeauducq: runtime: support boards without RTIO CRG
<GitHub191>
artiq/master 8fab789 Sebastien Bourdeauducq: runtime: support RTIO configurations without address (e.g. all simple TTL out)
<whitequark>
sb0: >cannot load kernel: ELF object has an unresolved symbol: dds_batch_exit
<cr1901_modern>
larsc: "unless it is for memory mapped devices" Isn't that the use case for most wishbone cores?
<larsc>
cr1901_modern: I mean something like DDR or SPI flash
<larsc>
bad wording, sorry
<larsc>
real memory that is mapped
<larsc>
not registers
<cr1901_modern>
Ahhh, that makes more sense. And makes it imperative that you have cache sitting between your CPU and WB interface since SPI flash is slow as molasses :P
<ssk1328>
_florent_: That was what I tried at first, but there are some other signals like ack and stb which needs to be connected in this case, and I was not sure about them
<ssk1328>
_florent_: Plus here connected source to two sinks was for testing, (floatmult.source is multiplying by 0.5, and further connecting it to both floadadd.sinks should give me output same as initial input)
<GitHub184>
[artiq] sbourdeauducq pushed 1 new commit to master: https://git.io/vKFWQ
<sb0>
regular wishbone doesn't do pipelining so each transaction (without comb feedback) will take 2 cycles
<sb0>
1st cycle cyc=stb=1, ack=0
<sb0>
2nd cycle cyc=stb=1, ack=1
<sb0>
3rd cycle cyc=stb=0 unless there's another transaction starting
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<whitequark>
I see
<whitequark>
I'll fix that and test it on real hardware tomorrow, then
<sb0>
kk. later there should be a trivial microcontroller that plays transactions from a list in block RAM, to set up the si5324 for 62.5MHz clock cleanup
<sb0>
by trivial microcontroller I mean some sort of two-instruction FSM-based processor