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whitequark >
gah. just spend more than an hour with the precedence of If(rd & x == 0
03:09
<
whitequark >
sb0: how do I make a 3'b000 ?
03:09
<
whitequark >
C(0)[0:4] didn't do it
03:20
<
sb0 >
something like C(0, 3)
03:22
<
whitequark >
that worked
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GitHub183 >
si5324_test/master e4c9ef2 whitequark: Use synchronous feedback for Wishbone.
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04:18
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whitequark >
sb0: ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7k325t'. Please run the Vivado License Manager for assistance in determining
04:18
<
whitequark >
this worked just a few days ago..
04:19
<
whitequark >
oh, I copied your license and it's fine now
04:26
<
sb0 >
yes, the new vivado version requires a new license. and before i got the kc705 code from you, i had generated a 30-day eval license
04:26
<
sb0 >
that probably expired
04:28
<
whitequark >
wtf, is vivado even slower than ise?..
04:29
<
sb0 >
about as slow
04:30
<
whitequark >
four minutes and counting
04:31
<
whitequark >
on basically the same thing ise did in 30 seconds, with six more buffers for the si5324 stuff
04:32
<
whitequark >
I guess "vivado for kc705's kintex7 chip" and "ise for pipistrello's spartan6 chip"
04:33
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sb0 >
you can compile with ise for the kc705 as well, if you have vivado problems
04:33
<
whitequark >
hm, I can try that...
04:34
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sb0 >
it's just kc705.Platform(toolchain="ise") iirc
04:47
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whitequark >
ok, testing it now.
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GitHub177 >
si5324_test/master cbecf89 whitequark: Use gateware to initialize Si5324 (WIP).
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04:47
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whitequark >
or rather going to the lab to test.
05:55
<
whitequark >
hm. doesn't work.
05:55
<
whitequark >
I wonder why.
06:05
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whitequark >
sb0: oh, looks like the reason vivado was that slow is because I've been driving cd_sys.rst without a BUFG
06:06
<
sb0 >
well you should not
06:07
<
whitequark >
it didn't even emit a warning.
06:07
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sb0 >
it may insert a BUFG automatically on the reset wire, but that's normally not required explicitly
06:08
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whitequark >
dunno then. well. i'm more interested in why this is broken rather than why vivado doesn't add a BUFG or whatever.
06:08
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whitequark >
the I2C multiplexer ACKs but Si5324 doesn't.
06:13
<
whitequark >
oh, it works now!
06:15
<
whitequark >
sb0: how do I tell your scope to measure ch2?
06:16
<
sb0 >
I don't remember exactly, but I think you should press the measure button and then there's a "source" menu that appears, select ch2 there
06:16
<
whitequark >
that worked
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GitHub40 >
si5324_test/master 85a4448 whitequark: Expose the I2C bus on XADC GPIOs, not just I2C master output.
06:18
<
GitHub40 >
si5324_test/master f465025 whitequark: Fix PCA9548 control word.
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whitequark >
sb0: it's done.
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GitHub137 >
si5324_test/master ac3dc5e whitequark: Reconfigure for 62.5MHz.
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06:37
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sb0 >
whitequark, thanks. i'll have a look shortly.
06:37
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sb0 >
did you sort out the vivado compilation issue (if any)?
06:42
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whitequark >
well it's fast now
06:42
<
whitequark >
"""""fast"""""
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07:31
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sb0 >
whitequark, can you update the sequencer unittest?
07:31
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whitequark >
it's not really a unittest
07:32
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whitequark >
wait, update? there isn't anything, not even a testbench
07:44
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whitequark >
sb0: do you want me to write a testbench for the sequencer (i.e. something to output the .vcd)? or do you want me to write a unittest (i.e. something programmatically check the result)?
08:00
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whitequark >
that's a weirdly written test
08:01
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sb0 >
what's wrong with it?
08:01
<
whitequark >
no check of IP
08:01
<
whitequark >
instruction pointer
08:04
<
whitequark >
ah well.
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GitHub182 >
si5324_test/master 3fd3905 whitequark: Add test for Sequencer.
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08:05
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sb0 >
if IP is wrong, the produced bus transactions are going to be wrong as well...
08:05
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sb0 >
and the design is simple enough that there aren't so many ways to get IP wrong
08:05
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whitequark >
yes. i'm saying it's weirdly written because "IP is wrong" is way easier to start debugging than "bus transactions are wrong"
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whitequark >
sb0: is that all for now?
08:21
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whitequark >
i'm going to do some merge work on solvespace then
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08:22
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sb0 >
bus.dat_r is don't care outside transactions
08:23
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sb0 >
so the only thing it should depend on is the address
08:23
<
whitequark >
then you couldn't read the divisor..
08:24
<
whitequark >
you mean 182?
08:24
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sb0 >
you can just organize the ifs as: If(bus.cyc & bus.stb & ~bus.ack, bus.ack.eq(1), If(bus.we, ...).Else(...))
08:24
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sb0 >
well without the .Else(), I guess
08:25
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whitequark >
I don't see how that works
08:25
<
sb0 >
it should simply be: sync += If(adr == 0, bus.dat_r.eq(...)), If(adr == 1, bus.dat_r.eq(...))
08:25
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sb0 >
so you remove the control signals from the dat_r generation, where they are not needed
08:25
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whitequark >
bus.cyc=0 bus.stb=0 bus.we=1
08:25
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whitequark >
then that would count as a write but it shouldn't
08:27
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sb0 >
no, the If(bus.we, ...) is inside the If(bus.cyc ...)
08:30
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whitequark >
nah, that won't work because of how i strobe read/write/etc
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GitHub78 >
si5324_test/master 9662c92 whitequark: I2CMaster: simplify wishbone read logic.
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08:39
<
whitequark >
sb0: fixed dat_r
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GitHub87 >
artiq/master 92f3757 Robert Jordens: spi: give wb-reads a register level
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cr1901_modern >
sb0: Can we turn off the synthesis on/off directives in migen?
16:00
<
cr1901_modern >
sb0: Because yosys complains anytime they're there, and clifford won't add an option to suppress them
16:00
<
cr1901_modern >
it's for the IceStorm backend only that I would want to turn them off, or replace them with `ifdef whatever
16:01
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sb0 >
why not actually
*support* them? even though they're hacky, they're pretty much a de-facto standard
16:02
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cr1901_modern >
yosys DOES support them, it just complains when they're there :P.
16:02
<
cr1901_modern >
I just wanted a way to suppress the messages as in "I know what I'm doing, leave me alone"
16:13
<
larsc >
run the files through sed as a preprocessor ;)
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GitHub78 >
artiq/master e7d6ad2 Robert Jordens: browser: cleanup dir/file restore, closes #527
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