sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/13c6e96760d8486b8ba0349a843066a05a9ecccf
<GitHub> artiq/master 13c6e96 whitequark: firmware: implement dyld::Library::rebind.
<bb-m-labs> build #422 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/422
<bb-m-labs> build #428 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/428 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #1339 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1339 blamelist: whitequark <whitequark@whitequark.org>
<whitequark> sb0: ERROR: test_start_ping_stop_controller (test_ctlmgr.ControllerCase)
<whitequark> seems like your area
<whitequark> sb0: btw what do you think of superh j2?
<cr1901_modern> whitequark: mithro asked me to add that to LiteX and I plan to port it to MiSoC if sb0 would accept the port
<cr1901_modern> it has good code density, mature toolchain, can run linux right away (MMUless)
<cr1901_modern> AFAICT it's smaller than lm32
<whitequark> well lm32 has an mmu these days
<cr1901_modern> Who uses it?
<whitequark> and or1k also does. you'd need an sh4 core for parity
<sb0> whitequark, I don't really know about superh j2. why?
<cr1901_modern> ysionnea1 was working on a BSD port (BSD doesn't have noMMU), but there's no linux port of it yet
<cr1901_modern> disadvantages: shift-add multiplier, delay slots
<whitequark> sb0: mature toolchain and very high density
<sb0> is the lm32 mmu tested?
<cr1901_modern> delay slot disadvantage *kinda* mitigated by code density
<sb0> whitequark, okay, but what for?
<whitequark> sb0: artiq?
<whitequark> I'm not suggesting migrating to it right now
<cr1901_modern> sb0: If you accept I MiSoC port, I will port it for you
<sb0> what's the end user improvement over or1k?
<whitequark> less time spent fighting or1k issues
<cr1901_modern> I might even do it anyway
<whitequark> oh hang on, llvm lacks an sh backend
<whitequark> nevermind
<cr1901_modern> that too
<cr1901_modern> although one was started
<sb0> pretty sure there is a crapload of sh issues as well
<sb0> anything non-x86 or non-arm breaks the toolchain
<sb0> well even arm has bugs sometimes
<whitequark> sb0: debian largely works on sh
<whitequark> but not on or1k
<cr1901_modern> whitequark: an SH port of llvm *is* in progress I believe? /join #j-core for more info?
<whitequark> that's not interesting if it's not upstream and CI'd
<cr1901_modern> or1k isn't
<whitequark> the idea is let other people do the work
<cr1901_modern> ?*
<whitequark> yes. so it's not an improvement.
<cr1901_modern> Oh well, all the open archs seem to be focused on gcc right now, except o1rk
<cr1901_modern> (Well, lm32 is stagnant)
<cr1901_modern> I guess gcc is an easier port then (or doesn't require as much time/labor/money to do)
<whitequark> inertia, I think
<whitequark> clang is still relatively new
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<cr1901_modern> that's also prob very true.
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<GitHub> [artiq] sbourdeauducq commented on issue #562: Remaining steps:... https://github.com/m-labs/artiq/issues/562#issuecomment-282458954
<sb0> do we put DRTIO on CI? it would require compiling two more bitstreams and flashing two KC705s every time...
<sb0> unless there is some sort of smart caching implemented
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<sb0> whitequark, what is buffering like in smoltcp? e.g. if I call write_u8 10 times, does it send 10 packets or aggregates the data into one?
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<mithro> Does misoc currently work on Python 3.6?
<sb0> if you apply the patch in the migen issues it should
<sb0> mithro, if would be nice if you tested it and cleaned it up
<mithro> ?
<sb0> mithro, yes
<mithro> sb0: I doubt I'm going to get a chance to look at it for atleast a week, so just going to force my build scripts to make conda go back to 3.5 for now
<GitHub> [artiq] sbourdeauducq opened issue #673: make core device more resilient to network/host problems https://github.com/m-labs/artiq/issues/673
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<whitequark> sb0: re DRTIO: good question
<whitequark> IMO builds are slow enough already...
<whitequark> re buffering: if you call write_u8 ten times, it will not send ten packets
<whitequark> it'll buffer them. in fact that path is cheap enough that adding a BufWriter (as it's recommended for a hosted TcpSocket) generally results in degraded performance and not improved
<sb0> okay, so when does it send them?
<whitequark> next poll
<GitHub> [artiq] whitequark commented on issue #673: > If the host begins a message but does not complete it, any kernel CPU messages and watchdogs should be processed.... https://github.com/m-labs/artiq/issues/673#issuecomment-282481576
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<GitHub> [artiq] sbourdeauducq commented on issue #673: > This seems quite troublesome to implement.... https://github.com/m-labs/artiq/issues/673#issuecomment-282481647
<GitHub> [artiq] whitequark commented on issue #673: > This worked with the C runtime.... https://github.com/m-labs/artiq/issues/673#issuecomment-282481732
<GitHub> [artiq] sbourdeauducq commented on issue #673: Why not do it again? We have plenty of RAM. https://github.com/m-labs/artiq/issues/673#issuecomment-282481753
<GitHub> [artiq] whitequark commented on issue #673: That pessimizes large RPCs. We have to spend the RAM twice: once on the comms CPU (to buffer the packet), then on the kernel CPU (to actually unpack it). And every time someone complains, we need to do the layout change dance, which is what prompted me to fix it.... https://github.com/m-labs/artiq/issues/673#issuecomment-282482059
<GitHub> [artiq] whitequark commented on issue #673: I suppose one way we could fix this without changing the networking code is add a separate watchdog thread that interrupts the session thread if the watchdog ever expires. But this is annoying because of all the data sharing. https://github.com/m-labs/artiq/issues/673#issuecomment-282482113
<whitequark> sb0: do I understand it right that the DMA engine can DMA from any memory region?
<whitequark> if yes, we don't need to keep the DMA mapping strictly linear
<whitequark> it can just live in kernel CPU's memory space as usual
<GitHub> [artiq] klickverbot commented on issue #673: You could also do the message processing in a fiber, context-switching back to normal execution every time you block waiting for input. Then again, requiring 2 x max_message_size in RAM isn't unreasonable, especially since you usually have to unpack the contents of the message somewhere else as well (making it 3x anyway). You could also think about application-side chunking for very large datasets, if that i
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<GitHub> [artiq] klickverbot commented on issue #673: (Fibers/green threads/… would also give you proper handling of multiple connections for free, although I must admit I'm not quite sure what the current story with the Rust runtime is there.) https://github.com/m-labs/artiq/issues/673#issuecomment-282487822
<GitHub> [artiq] whitequark commented on issue #673: We already use cooperative multitasking on the core device. That was one of the major points of migration to Rust.... https://github.com/m-labs/artiq/issues/673#issuecomment-282487910
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<GitHub> [artiq] whitequark commented on commit bc36bda: You shouldn't do this, since you get duplicate kernel_proto types. Remove it and the compilation still succeeds anyway. https://github.com/m-labs/artiq/commit/bc36bda94abb6841ad0716004430b23114989046#commitcomment-21051426
<GitHub> [artiq] whitequark pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/13c6e96760d8...2a81819eb0d3
<GitHub> artiq/master 2a81819 whitequark: firmware: restructure to avoid #[path = "..."] mod ...;...
<GitHub> artiq/master d04e611 whitequark: firmware, compiler: rename rpc functions to be more consistent.
<bb-m-labs> build #423 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/423
<bb-m-labs> build #429 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/429 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #1340 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1340 blamelist: whitequark <whitequark@whitequark.org>
<GitHub> [artiq] trxw opened issue #674: Problem with Pipistrello board https://github.com/m-labs/artiq/issues/674
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