15:39 <sb0> whitequark, have you tried hardcoding DMA records and SDRAM words into the gateware to narrow down the bug?

15:40 <sb0> another thing you could try is run the DMA core simulation with the exact same SDRAM words as on the board

15:40 <sb0> the SDRAM words are big endian (LSBs on high addresses)

16:06 <sb0> whitequark, have you seen what the pack() function does in the test bench? in the end, it's not little endian.

16:06 <sb0> I'd be fine with flipping the bits in gateware, the current encoding is a tad messy

16:10 <GitHub> [artiq] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/artiq/compare/1dbfaf5ad03c...d1b9f9d73716

16:10 <GitHub> artiq/master d1b9f9d Sebastien Bourdeauducq: drtio: rt_packets → rt_packet

16:10 <GitHub> artiq/master 6b7c781 Sebastien Bourdeauducq: drtio: introduce 'standard request' interface in RT packet layer

16:10 <GitHub> artiq/master 2b8729f Sebastien Bourdeauducq: drtio: clear any read request on satellite reset

16:24 <brevy1> Hello guys, I am new to most of this. I have misoc working and I can run the minispartan6.py but I need to modify it to match my spartan6 xc6slx16. What do I need to edit for this?

16:32 <sb0> brevy1, the pin/fpga definition files are in migen/build/platforms

16:33 <sb0> and then you have the soc design in misoc/targets

16:35 <bb-m-labs> build #462 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/462

16:36 <brevy1> sb0 I do not have a platforms dir inside of build

16:37 <sb0> *migen*/build

16:37 <brevy1> the problem is the bit file it generates is for a xc6slx9 and I need a xc6slx16 version

16:38 <sb0> is it the only change on your board? slx9 to slx16?

16:38 <sb0> pin compatible?

16:39 <brevy1> I will need to dig into the data sheets, but It was a start

16:41 <brevy1> I think so

16:43 <bb-m-labs> build #438 of artiq-win64-test is complete: Failure [failed python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/438 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

16:44 <bb-m-labs> build #1392 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1392 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

16:46 <brevy1> http://www.digikey.com/product-detail/en/xilinx-inc/XC6SLX9-2CSG225I/122-1949-ND/2339914 vs http://www.digikey.com/product-detail/en/xilinx-inc/XC6SLX16-2CSG324C/122-1671-ND/2408281

16:54 <brevy1> When you say pin/fpga definition do you mean .ucf files? I am not sure why the platform directory is missing.

17:08 <brevy1> Thanks sb0, I miss read migen for misoc..

17:08 <brevy1> really great project, thanks for the help.

17:25 <whitequark> sb0: no, I haven't tried

17:26 <whitequark> SDRAM words being flipped *might* actually be what's happening

17:26 <whitequark> let me see