sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> rjo, whitequark I have ordered a new CPU for the buildbot, will probably install it Monday
<sb0> or this weekend, depending when it arrives
<rjo> sb0: ack.
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<whitequark> sb0: excellent
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<whitequark> sb0: hm, weird
<whitequark> I redid the arbiter but now the DMA core hangs *every* time, inexplicabl
<sb0> hangs where?
<whitequark> enable_read() never comes down, I have not yet instrumented the FSMs again
<sb0> did it pass timing?
<GitHub> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/391660e5454a31c5e93053922c056196616f5b11
<GitHub> artiq/master 391660e whitequark: gateware: simplify the CRI arbiter to use a plain mux.
<whitequark> sb0: does vivado save a log somewhere? tmux ate the backscroll
<whitequark> another question: is there some flag we can set that makes vivado just outright fail if the timing doesn't pass?
<whitequark> (why is that not the case in first place?!)
<bb-m-labs> build #1442 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1442 blamelist: whitequark <whitequark@whitequark.org>
<sb0> whitequark, you have mapped the cri_con CSRs to the comms CPU
<sb0> this should go to the kernel CPU
<sb0> whitequark, yes, vivado saves a log (vivado.jou iirc) and there is also the timing report file
<sb0> I don't know about such an optio
<whitequark> sb0: oh
<whitequark> that would do it
<whitequark> sb0: actually, why did it just do nothing?
<whitequark> I'd expect an exception
<GitHub> [artiq] sbourdeauducq commented on commit 391660e: ``CRISwitch`` would be a better name I think. https://github.com/m-labs/artiq/commit/391660e5454a31c5e93053922c056196616f5b11#commitcomment-21639773
<sb0> whitequark, yes, it should have done nothing
<whitequark> oh?
<sb0> whitequark, what exception and why?
<whitequark> access to a nonexistent CSR
<whitequark> so a bus error or something
<sb0> ah. this. i thought you were talking about the DMA core
<sb0> detecting non-existent CSRs requires additional logic that isn't there
<sb0> and if adding it, it should be done in a way that doesn't slow down the sluggish xilinx fpgas any further
<whitequark> okay
<whitequark> does adding cri_con at 0x70000000 sound ok?
<whitequark> oh nvm it detects conflicts
<whitequark> regarding vivado not being able to fail the build on timing failure: that's idiotic
<whitequark> I can't believe this isn't the single most obvious feature to add wanted by anyone ever touching an FPGA
<whitequark> do they use their own software?
<rjo> afaict automated building and ci on fpgas the way we do it is "very exotic".
<rjo> people tend to babysit it.
<whitequark> even when I build manually I have very little desire to read the log every time to make sure the PAR didn't strike an instability
<sb0> ISE printed a clear message "All constraints were met" (or not) at the end, but Vivado does not
<whitequark> sb0: this is interesting
<whitequark> https://hastebin.com/bujoqukima.py still hangs
<whitequark> but it hangs in a more interesting way
<whitequark> oh nevermind
<bb-m-labs> build #1443 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1443 blamelist: whitequark <whitequark@whitequark.org>
<whitequark> sb0: doesn't hang
<whitequark> in fact the DMA core now works quite nicely
<sb0> good! finally
<whitequark> well the question is why?
<whitequark> meet the new switch, essentially the same as the old switch
<whitequark> there is no functional difference given the way we drive it
<sb0> I would guess xilinx miscompilation, or timing failure not found by the xilinx timing models
<sb0> the second option is less likely considering that the freeze spray did nothing
<sb0> whitequark, so, there's still #700
<whitequark> sure
<whitequark> I'm working on that already
<sb0> after that there's pdq3 and a bunch of various things. https://github.com/m-labs/artiq/milestone/5
<bb-m-labs> build #1444 of artiq is complete: Exception [exception interrupted] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1444 blamelist: whitequark <whitequark@whitequark.org>
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<GitHub> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/56918fb37531...674bf82f3a6a
<GitHub> artiq/master 674bf82 Sebastien Bourdeauducq: gateware: add cri_con CSRs to all DMA-capable targets
<GitHub> artiq/master 5e3aef4 Sebastien Bourdeauducq: drtio: support collision/replace + detect sequence errors at satellite
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<bb-m-labs> build #506 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/506
<bb-m-labs> build #451 of artiq-win64-test is complete: Warnings [warnings python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/451 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1445 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1445
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<bb-m-labs> build #507 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/507
<bb-m-labs> build #452 of artiq-win64-test is complete: Warnings [warnings python_unittest] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/452 blamelist: whitequark <whitequark@whitequark.org>
<bb-m-labs> build #1446 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1446
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