sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> whitequark, is there still some blocker for DMA?
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<whitequark> sb0: no
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<sb0> _florent_, how is the wishbone bridge coming along?
<_florent_> sb0: basic functionnality is working, with buffered writes you wanted. I now need to look at corner case (error reporting, etc...) and clean it up
<sb0> _florent_, does it work on the board?
<sb0> how can I test it?
<sb0> etherbone?
<_florent_> sb0: that's derivated from etherbone
<_florent_> sb0: I'll need the artiq hardware to finish things and provides example
<sb0> is it exactly the etherbone protocol? if not, it should be called differently
<_florent_> sb0: yes that's the etherbone protocol
<_florent_> sb0: just that it's limited (no probing, only 1 record per packet)
<_florent_> sb0: do you still expect to have the hardware at the end of the month?
<sb0> I'll ping Greg, but I don't think so
<_florent_> ok good
<whitequark> sb0: 6.5ns per playback with handles
<whitequark> erm, us
<sb0> whitequark, okay, that's better
<sb0> still a bit on the slow side though, do you have an idea why?
<whitequark> not yet
<sb0> _florent_, to avoid accumulating delays, maybe we test this on some other boards
<_florent_> sb0: for the etherbone stuf, I'm not worried, I'm already using it over udp and usb
<_florent_> stuff
<_florent_> sb0: I'll probably be able to test it on hardware before having the artiq gateware
<_florent_> sb0: I just need to finish the phase detector stuff
<_florent_> sb0: it seems with the arty board I have we are not able to use the LVDS with PMODs
<sb0> well, vivado breakdowns and obscure gateware bugs are rather frequent
<_florent_> sb0: I'm going to try with another board (nexys_video or a custom one)
<sb0> and the wishbone bridge is one of the first things we're going to need to test sayma
<_florent_> sb0: I know, and I was planning to work on it this week
<whitequark> sb0: https://hastebin.com/sudirotade.pl the core of the loop
<whitequark> it's basically only refilling the argument registers from callee-saved registers
<whitequark> needless to say dma_playback doesn't do anything extraneous either, sec
<_florent_> sb0: just for info, my plan for the week was to getting the phase detector working on a HDMI RX design I'm working on: https://github.com/enjoy-digital/litevideo/blob/master/test/nexys_video_loopback.py
<_florent_> sb0: and then re-use that for ARTIQ and test it on hardware
<_florent_> sb0: the HDMI RX design is easier to work with (since you have visual results)
<_florent_> sb0: I'll keep you informed, but understand your fears and I'm trying to test all I can before receiving the hardware
<whitequark> well I guess I could shave off two instructions by removing the assert at the beginning
<GitHub> [artiq] whitequark pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/41c4de45563c0807389278bc0c742e0c92c9415c
<GitHub> artiq/master 41c4de4 whitequark: DMA: add API for a much faster replay using handles.
<sb0> _florent_, ok thanks
<GitHub> [artiq] whitequark closed issue #712: dma sequence recording slow https://github.com/m-labs/artiq/issues/712
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<sb0> bb-m-labs, force build artiq
<bb-m-labs> build #1466 forced
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #520 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/520
<bb-m-labs> build #1466 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1466
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