Topic for #milkymist is now Radical Tech Coalition :: Milkymist One, Migen, Milkymist SoC & Flickernoise :: Logs: http://en.qi-hardware.com/mmlogs
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<GitHub171> [scripts] xiangfu pushed 3 new commits to master: http://git.io/ehBOdA
<GitHub171> [scripts/master] reflash_m1.sh use only one fjmem, cleanup - Xiangfu Liu
<GitHub171> [scripts/master] reflash_m1.sh update to latest release for rc3 - Xiangfu Liu
<GitHub171> [scripts/master] reflash_m1.sh bump version - Xiangfu Liu
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<GitHub3> [autotest-m1] xiangfu pushed 1 new commit to master: http://git.io/sMe-YA
<GitHub3> [autotest-m1/master] fix typo, should use libmath.a - Xiangfu Liu
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<barbu-uucp> azonenberg: you might like this http://raintown.org/lava/
<azonenberg> "These pages assume a good understanding of Xilinx's Virtex FPGA architecture and of the Haskell lazy functional programming language. The number of people that know about both can easily fit inside a medium sized elevator"
<azonenberg> Looks interesting but i question whether it's too complex to be of any use lol
<barbu-uucp> you find it complex?
<azonenberg> I understand what they're doing
<barbu-uucp> it's not any worse than your pipelined adder :)
<azonenberg> i just think that often you dont care about placement
<azonenberg> But OTOH, mixing that with verilog or vhdl
<azonenberg> for the most speed critical parts of the circuit
<azonenberg> Might well be worth doing
<barbu-uucp> what could be cool would be a high-level placer
<barbu-uucp> something that operates on top of lava and automatically generates the lava-level placement constraints
<azonenberg> HmmI definitely want to play with it, thats for sure
<azonenberg> Is there a back end for spartan chips?
<barbu-uucp> though lava itself already has a good deal of functions that generate placements
<barbu-uucp> so it's not _that_ bad :)
<barbu-uucp> no, I don't think so. you'd have to write it :)
<barbu-uucp> some things have changed, e.g. the carry chains are more complex now
<azonenberg> yeah
<barbu-uucp> and 6-LUT architectures can build efficient ternary adders with one chain
<barbu-uucp> so the adder tree example needs some revamping
<azonenberg> Well, i am definitely going to fool around with it though
<azonenberg> As well as manually doing low level (LUT and CLB based) FPGA dev at some point
<azonenberg> I intend to learn the architecture inside out
<barbu-uucp> azonenberg: you can also try to combine Lava with a DIY router (not too hard to do using the XDL descriptions) and the Recobus bitstream generator
<barbu-uucp> lava to bitstream in 100ms, without any xilinx tool :)
<azonenberg> lol
<azonenberg> I do want a free toolhain
<azonenberg> And one optimized for extreme performance wouldn't hurt
<azonenberg> Something to look into when i have free time, perhaps
<azonenberg> But I have a doctoral thesis in *computer science* to finish first
<azonenberg> Maybe then i can think about doing one in EE :p
<barbu-uucp> I wonder how hard it would be to run Haskell on the LM32
<barbu-uucp> cpython is messy, lots of dynamic code loading
<barbu-uucp> ruby is super easy
<azonenberg> No idea, i havent used lm32
<azonenberg> I'm actually writing my own softcore optimized for my specific workloads
<azonenberg> 2-way superscalar barrel processor
<azonenberg> 16 threads, it issues two instructions from each one in a round-robin fashion
<azonenberg> then goes back and issues two from the first thread again etc
<azonenberg> that allows a 16-stage pipeline with no stalls
<barbu-uucp> well, the problem is actually not LM32 itself, it's more about the operating systems
<azonenberg> in reality some of the FPU is 32 stages so i need to have one delay slot in which you can't use the output of the fdiv/fsqrt or it'll stall
<barbu-uucp> python happily calls dl*() all over the place, that neither RTEMS or Linux implements properly
<azonenberg> lol
<azonenberg> I havent even started to think about the OS i'd run on this guy
<azonenberg> But it'd have to be hardware multithreading aware
<azonenberg> My roommate says that lava looks like the C of HDLs
<azonenberg> as in, getting close to the architecture for maximum performance
<azonenberg> while still maintaining some level of abstraction for ease of development
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<GitHub185> [migen] sbourdeauducq pushed 2 new commits to master: https://github.com/milkymist/migen/compare/0ea7a9b...c840848
<GitHub185> [migen/master] wishbone: decoder: fix slave cyc generation in registered mode - Sebastien Bourdeauducq
<GitHub185> [migen/master] verilog: use blocking assignment in combinatorial process - Sebastien Bourdeauducq
<GitHub167> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/6f7a35e0a34a35cb1779e0e214aafce142ddbbd7
<GitHub167> [migen/master] examples: Wishbone interconnect test bench - Sebastien Bourdeauducq
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<GitHub110> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/22d03b4943a3bb6339c03a0607c0893410766609
<GitHub110> [migen/master] timeline: only trigger in rest state - Sebastien Bourdeauducq
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<lekernel> grmbl... icarus verilog is still incapable of simulating lm32
<stekern> really? why's that?
<lekernel> it uses tons of macros and generate statements, and this confuses iverilog's little brain
<stekern> I see
<stekern> I haven't noticed any major issues with iverilog and generate statements, but maybe it's just particular ones that it gets confused by :)
<lekernel> I can't get my migen-built soc to work, and the absence of a suitable simulator doesn't help
<lekernel> maybe I should get a cracked modelsim ...
<lekernel> or maybe xilinx isim would do the trick... I haven't tried it yet
<stekern> it's slow as hell if you don't have the payed license and your design is larger than 'blink-a-led'
<stekern> *paid
<lekernel> well I just want to fix this one annoying bug
<lekernel> ERROR:HDLCompiler:1654 - "../verilog/lm32/lm32_multiplier_spartan6.v" Line 47: Instantiating <D1> from unknown module <DSP48A1>
<lekernel> phew
<lekernel> "Using glbl as top_name is mandatory if behavioral design instantiates UNISIM primitiv es" .....
<lekernel> yay! got it to work!
<kristianpaul> good, what was it? :)
<lekernel> a stupid bug in the flash controller
<lekernel> it would still use the address of the 1st request when 2 wishbone requests were sent without any "dead time"
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<kristianpaul> btw this m1gen will support multilple lm32 cores;) ?
<lekernel> if you add a parameter to the LM32 core that gives an "ID number" to each core, and if you don't need cache coherency, yes, it's easy
<stekern> lekernel: that looks pretty nifty
<GitHub18> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/929cc9807020ebaba3c1a6a77e786f5a8160c962
<GitHub18> [migen/master] wishbone2csr: wait for WB deack - Sebastien Bourdeauducq
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<whitequark> hmm
<whitequark> I guess I need to have ise webpack to do any work on MM core?
<lekernel> what is "MM core"?
<whitequark> the firmware of FPGA
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<whitequark> ise webpack license is like an agreement with satan
<lekernel> whitequark: just write a replacement then
<whitequark> lekernel: I'm not complaining
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<kristianpaul> mm/milkymist but is not a core is a SoC :)
<whitequark> I don't understand almost anything in fpga world.
<whitequark> can anyone say what do I need to do to get maybe a simulated lm32 core or whatever?
<kristianpaul> fpga4fun is a good start, plus getting a m1 :)
<whitequark> well
<whitequark> $500 isn't something I can spend right now
<kristianpaul> whitequark: you can run qemu for soft
<whitequark> kristianpaul: I know how software works, thanks :)
<kristianpaul> *g*
<whitequark> wolfspraul expects me to write MMU for LM32.
<whitequark> well
<whitequark> he is quite optimistic then
<whitequark> but still
<kristianpaul> :)
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<n0carri3r> hey all
<n0carri3r> just stopping by.. curious about the MIDIUSB :)
<kristianpaul> hi
<n0carri3r> hi
<whitequark> is milkymist-ng the repository I should use?
<whitequark> it's created 6 hours ago, hmm
<kristianpaul> he dont think so, not yet tought
<kristianpaul> just milkymsit whitequark
<whitequark> kristianpaul: ah okay. I think I'll start with fpga4fun first
<kristianpaul> whitequark: check this http://www.xess.com/appnotes/FpgasNowWhatBook.pdf
<whitequark> a friend offers to lend me a nexys2
<whitequark> I guess it's fine for tutorials
<kristianpaul> yes
<kristianpaul> also for porting M1 to it
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<n0carri3r> gotta run bbiab
<whitequark> kristianpaul: huh? it does not have any of m1 peripherals
<kristianpaul> a FPGA
<whitequark> kristianpaul: I'm not sure what do you mean...
<wpwrak> good news: i liberated my pre-rc4 from customs
<stekern> well, it's free hardware after all :P
<whitequark> wpwrak: I wonder if that's an euphemism like "eliminate"
<whitequark> are they still alive? (I hope no, but...)
<wpwrak> well, today it wasn't too bad. only about 3 hours from arrival to departure
<wpwrak> and no surprise costs
<kristianpaul> wpwrak: congrats !
<kristianpaul> no adidional feeds either?
<kristianpaul> whitequark: to get started you dont need a fully capable board
<kristianpaul> just and fpga you can program and a serial port
<whitequark> kristianpaul: well, I've relocated recently
<whitequark> I don't even have a soldering iron. almost nothing, actually
<whitequark> not even a single atmega :)
<whitequark> so I
<whitequark> *I'm thinking what can I get the cheapest and quickiest way
<kristianpaul> you said you borrowed a nexsys2 dont you?
<whitequark> not yet
<whitequark> it's 00:45 here...
<whitequark> 15 minutes more, and there will be no working public transport
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<whitequark> kristianpaul: okay. I've read several tutorials (including the NowWhat!?)
<whitequark> and assembled something that works in simulator
<whitequark> I think I'm starting to get the idea of how this stuff works.
<mwalle> lekernel: btw pep8 defines function names to be lower_case_with_underscores()
<whitequark> sigh. python.